Verilog PWM code module

LIP1122CORE_irpwn.doc
CVS\Entries
...\Repository
...\Root
hdl\irpwm_ir_nec.v
...\irpwm_ir_rc5.v
...\irpwm_pwm.v
...\CVS\Entries
...\...\Repository
...\...\Root
PWM_1\.untf
.....\automake.log
.....\irpwm.v
.....\irpwm_ir_nec.bld
.....\irpwm_ir_nec.cel
.....\irpwm_ir_nec.cmd_log
.....\irpwm_ir_nec.lso
.....\irpwm_ir_nec.ngc
.....\irpwm_ir_nec.ngd
.....\irpwm_ir_nec.ngr
.....\irpwm_ir_nec.prj
.....\irpwm_ir_nec.stx
.....\irpwm_ir_nec.syr
.....\irpwm_ir_nec.ucf
.....\irpwm_ir_nec.v
.....\irpwm_ir_nec_summary.html
.....\irpwm_ir_nec_vhdl.prj
.....\irpwm_ir_rc5.v
.....\irpwm_pwm.v
.....\irpwm_summary.html
.....\Project.dhp
.....\PWM_1.dhp
.....\PWM_1.ise
.....\PWM_1.ise_ISE_Backup
.....\__projnav.log
.....\.........\ednTOngd_tcl.rsp
.....\.........\irpwm_ir_nec.xst
.....\.........\parentCreateTimingConstraintsApp_tcl.rsp
.....\.........\PWM_1.gfl
.....\.........\PWM_1_flowplus.gfl
.....\.........\runXst_tcl.rsp
.....\.........\sumrpt_tcl.rsp
.....\.ngo\netlist.lst
.....\xst\work\hdllib.ref
.....\...\....\vlg5A\irpwm__ir__nec.bin
syn\CVS\Entries
...\...\Repository
...\...\Root
...\artisan_tsmc15lv\.cvsignore
...\................\irpwm_extract_netlist.tcl
...\................\irpwm_formal_verif.tcl
...\................\irpwm_report.tcl
...\................\irpwm_setup.tcl
...\................\irpwm_simple_compile.tcl
...\................\Makefile
...\................\work_lib\irpwm%verilog.syn
...\................\........\irpwm%verilog__verilog.syn
...\................\........\IRPWM.mr
...\................\........\irpwm_ir_nec%verilog.syn
...\................\........\irpwm_ir_nec%verilog__verilog.syn
...\................\........\IRPWM_IR_NEC.mr
...\................\........\irpwm_ir_rc5%verilog.syn
...\................\........\irpwm_ir_rc5%verilog__verilog.syn
...\................\........\IRPWM_IR_RC5.mr
...\................\........\irpwm_pwm%verilog.syn
...\................\........\irpwm_pwm%verilog__verilog.syn
...\................\........\IRPWM_PWM.mr
...\................\synthesis\irpwm.db
...\................\.........\irpwm.v
...\................\.........\irpwm_area.rpt
...\................\.........\irpwm_cell.rpt
...\................\.........\irpwm_constraint.rpt
...\................\.........\irpwm_net.rpt
...\................\.........\irpwm_qor.rpt
...\................\.........\irpwm_timing.rpt
...\................\CVS\Entries
...\................\...\Repository
...\................\...\Root
irpwm.v
PWM_1\xst\dump.xst\irpwm_ir_nec.prj\ngx\opt
.....\...\........\................\...\notopt
.....\...\........\................\ngx
.....\...\work\vlg5A
.....\...\dump.xst\irpwm_ir_nec.prj
.....\...\work
.....\...\dump.xst
syn\artisan_tsmc15lv\work_lib
...\................\synthesis
...\................\CVS
hdl\CVS
PWM_1\__projnav
.....\_xmsgs
.....\_ngo
.....\xst
syn\CVS
...\artisan_tsmc15lv
CVS
hdl
PWM_1
syn

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