Based on VHDL language, to achieve simple control of ADC0809. ADC0809 no internal clock, an external 10KHz ~ 1290Hz clock signal, where the FPGA system clock (50MHz) divided by 256 get clk1 (195KHz) as the conversion clock ADC0809

EXP2-ADC\adc.dhp
........\adc.ipf
........\adc.ise
........\adc.ise_ISE_Backup
........\adc0809.bgn
........\adc0809.bit
........\adc0809.bld
........\adc0809.cmd_log
........\adc0809.drc
........\adc0809.lso
........\adc0809.mrp
........\adc0809.nc1
........\adc0809.ncd
........\adc0809.ngc
........\adc0809.ngd
........\adc0809.ngm
........\adc0809.ngr
........\adc0809.pad
........\adc0809.pad_txt
........\adc0809.par
........\adc0809.pcf
........\adc0809.placed_ncd_tracker
........\adc0809.prj
........\adc0809.routed_ncd_tracker
........\adc0809.stx
........\adc0809.syr
........\adc0809.twr
........\adc0809.twx
........\adc0809.ucf
........\adc0809.ucf.untf
........\adc0809.ut
........\ADC0809.vhd
........\adc0809.xpi
........\adc0809_last_par.ncd
........\adc0809_map.ncd
........\adc0809_map.ngm
........\adc0809_pad.csv
........\adc0809_pad.txt
........\adc0809_summary.html
........\bitgen.ut
........\Project.dhp
........\xst\work\hdllib.ref
........\...\....\hdpdeps.ref
........\...\....\sub00\vhpl00.vho
........\...\....\.....\vhpl01.vho
........\_impact.cmd
........\.ngo\netlist.lst
........\._projnav\adc.gfl
........\.........\adc0809.xst
........\.........\adc0809_ncdTOut_tcl.rsp
........\.........\adc_flowplus.gfl
........\.........\bitgen.rsp
........\.........\ednTOngd_tcl.rsp
........\.........\nc1TOncd_tcl.rsp
........\.........\parentEditConstraintsTextApp_tcl.rsp
........\.........\runXst_tcl.rsp
........\.........\sumrpt_tcl.rsp
........\xst\dump.xst\adc0809.prj\ngx\notopt
........\...\........\...........\...\opt
........\...\........\...........\ngx
........\...\........\adc0809.prj
........\...\work\sub00
........\...\dump.xst
........\...\work
........\xst
........\_ngo
........\_xmsgs
........\__projnav
EXP2-ADC

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