Ring is twisted to achieve a decimal counter, using verilog HDL language, Actel offers the LiberoFPGA development environment, the code is validated, the simulation in the ModelSim

74hc4017
........\component
........\constraint
........\coreconsole
........\designer
........\........\impl1
........\........\.....\model4017.dtf
........\........\.....\model4017_fp
........\........\.....\............\projectData
........\........\.....\simulation
........\........\.....\..........\postlayout
........\........\.....\..........\..........\model4017
........\........\.....\..........\..........\stimulus
........\........\.....\..........\..........\tb_clock_minmax
........\........\.....\..........\..........\testbench
........\........\.....\..........\..........\_temp
........\hdl
........\phy_synthesis
........\simulation
........\..........\postsynth
........\..........\.........\model4017
........\..........\.........\stimulus
........\..........\.........\tb_clock_minmax
........\..........\.........\testbench
........\..........\.........\_temp
........\..........\presynth
........\..........\........\model
........\..........\........\model4017
........\..........\........\stimulus
........\..........\........\tb_clock_minmax
........\..........\........\testbench
........\..........\........\_temp
........\smartgen
........\stimulus
........\synthesis
........\.........\backup
........\.........\coreip
........\.........\syntmp
........\viewdraw
........\........\sch
........\........\sym
........\........\vf
........\........\wir
........\4017_module.prj
........\designer\impl1\4017model.ide_des
........\........\.....\4017_module.ide_des
........\........\.....\designer.log
........\........\.....\designer_synth_check.log
........\........\.....\model.ide_des
........\........\.....\model4017.adb
........\........\.....\..........dtf\verify.log
........\........\.....\model4017.ide_des
........\........\.....\model4017.pdb
........\........\.....\model4017.pdb.depends
........\........\.....\model4017.tcl
........\........\.....\model4017_ba.sdf
........\........\.....\model4017_ba.sdf_max.csd
........\........\.....\model4017_ba.v
........\........\.....\..........fp\$$FlashPro_FPBBALTLPT1.L$$
........\........\.....\............\model4017.log
........\........\.....\............\model4017.pro
........\........\.....\............\projectData\model4017.pdb
........\........\.....\simulation\postlayout\model4017\verilog.psm
........\........\.....\..........\..........\.........\_primary.dat
........\........\.....\..........\..........\.........\_primary.dbs
........\........\.....\..........\..........\.........\_primary.vhd
........\........\.....\..........\..........\stimulus\verilog.psm
........\........\.....\..........\..........\........\_primary.dat
........\........\.....\..........\..........\........\_primary.dbs
........\........\.....\..........\..........\........\_primary.vhd
........\........\.....\..........\..........\tb_clock_minmax\verilog.psm
........\........\.....\..........\..........\...............\_primary.dat
........\........\.....\..........\..........\...............\_primary.dbs
........\........\.....\..........\..........\...............\_primary.vhd
........\........\.....\..........\..........\.estbench\verilog.psm
........\........\.....\..........\..........\.........\_primary.dat
........\........\.....\..........\..........\.........\_primary.dbs
........\........\.....\..........\..........\.........\_primary.vhd
........\........\.....\..........\..........\_info
........\........\.....\..........\..........\_vmake
........\hdl\4017_module.v
........\simulation\modelsim.ini
........\..........\modelsim.ini.sav
........\..........\modelsim.log
........\..........\postsynth\model4017\verilog.psm
........\..........\.........\.........\_primary.dat
........\..........\.........\.........\_primary.dbs
........\..........\.........\.........\_primary.vhd
........\..........\.........\stimulus\verilog.psm
........\..........\.........\........\_primary.dat
........\..........\.........\........\_primary.dbs
........\..........\.........\........\_primary.vhd
........\..........\.........\tb_clock_minmax\verilog.psm
........\..........\.........\.........

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