Sdram the Verilog file contains procedures and information are all of Sdram

sdram_paul\256Mb_sdr.pdf
..........\sdram_controller_verilog_lattice.pdf
..........\.................xm\docs\filelist.txt
..........\...................\....\readme.txt
..........\...................\....\user's guide.doc
..........\...................\par\xm\sdr_top.log
..........\...................\...\..\sdr_top.mrp
..........\...................\...\..\sdr_top.pad
..........\...................\...\..\sdr_top.par
..........\...................\...\..\sdr_top.prf
..........\...................\...\..\sdr_top.sdf
..........\...................\...\..\sdr_top.tcl
..........\...................\...\..\sdr_top.vo
..........\...................\...\..\sdr_top_overconstraint.twr
..........\...................\...\..\sdr_top_post.prf
..........\...................\...\..\sdr_top_post_route_trace.twr
..........\...................\simulation\readme.txt
..........\...................\..........\xm\modelsim\rtl\rtl_sim.log
..........\...................\..........\..\........\scripts\sdr_fsim.tcl
..........\...................\..........\..\........\.......\sdr_tsim.tcl
..........\...................\..........\..\........\timing\timing_sim.log
..........\...................\.ource\sdr_ctrl.v
..........\...................\......\sdr_data.v
..........\...................\......\sdr_par.v
..........\...................\......\sdr_sig.v
..........\...................\......\sdr_top.v
..........\...................\.ynthesis\xm\synplicity\rev_1\sdr_top.edn
..........\...................\.........\..\..........\.....\sdr_top.prf
..........\...................\.........\..\..........\.....\sdr_top.tlg
..........\...................\.........\..\..........\sdr_top.prd
..........\...................\.........\..\..........\sdr_top.prj
..........\...................\.........\..\..........\sdr_top.tcl
..........\...................\testbench\readme.txt
..........\...................\.........\sdr_tb.tf
..........\W986416_75.pdf
..........\sdram_controller_xm\simulation\xm\modelsim\rtl
..........\...................\..........\..\........\scripts
..........\...................\..........\..\........\timing
..........\...................\.ynthesis\xm\synplicity\rev_1
..........\...................\.imulation\xm\modelsim
..........\...................\.ynthesis\xm\synplicity
..........\...................\par\xm
..........\...................\simulation\xm
..........\...................\.ynthesis\xm
..........\...................\docs
..........\...................\par
..........\...................\simulation
..........\...................\source
..........\...................\synthesis
..........\...................\testbench
..........\sdram_controller_xm
sdram_paul

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