Tri-State Ethernet hdl source code for FPGA engineers

ethernet_tri_mode\web_uploads\ethernet_tri_mode\start.tcl
.................\...........\.................\.yn\syn.prj
.................\...........\.................\...\syn_altrea.prj
.................\...........\.................\...\syn_xilinx.prj
.................\...........\.................\.im\rtl_sim\ncsim_sim\script\batch_mode.tcl
.................\...........\.................\...\.......\.........\......\filesel.tcl
.................\...........\.................\...\.......\.........\......\run.tcl
.................\...........\.................\...\.......\.........\......\run_proc.tcl
.................\...........\.................\...\.......\.........\......\set_reg_data.tcl
.................\...........\.................\...\.......\.........\......\set_stimulus.tcl
.................\...........\.................\...\.......\.........\......\start_verify.tcl
.................\...........\.................\...\.......\.........\......\user_lib.tcl
.................\...........\.................\...\.......\.........\log\ncsim.log
.................\...........\.................\...\.......\.........\data\1000Mbps_duplex.vec
.................\...........\.................\...\.......\.........\....\100Mbps_duplex.vec
.................\...........\.................\...\.......\.........\....\10Mbps_duplex.vec
.................\...........\.................\...\.......\.........\....\46-50.ini
.................\...........\.................\...\.......\.........\....\batch.dat
.................\...........\.................\...\.......\.........\....\config.ini
.................\...........\.................\...\.......\.........\....\CPU.vec
.................\...........\.................\...\.......\.........\....\flow_ctrl.vec
.................\...........\.................\...\.......\.........\....\source_mac_replace.vec
.................\...........\.................\...\.......\.........\....\target_mac_check.vec
.................\...........\.................\...\.......\.........\bin\cds.lib
.................\...........\.................\...\.......\.........\...\com.nc
.................\...........\.................\...\.......\.........\...\config.ini
.................\...........\.................\...\.......\.........\...\hdl.var
.................\...........\.................\...\.......\.........\...\ip_32W_check.dll
.................\...........\.................\...\.......\.........\...\ip_32W_check_vpi.dll
.................\...........\.................\...\.......\.........\...\ip_32W_gen.dll
.................\...........\.................\...\.......\.........\...\ip_32W_gen_vpi.dll
.................\...........\.................\...\.......\.........\...\sim.nc
.................\...........\.................\...\.......\.........\...\sim_only.nc
.................\...........\.................\...\.......\.........\...\vlog.list
.................\...........\.................\rtl\verilog\Clk_ctrl.v
.................\...........\.................\...\.......\eth_miim.v
.................\...........\.................\...\.......\header.v
.................\...........\.................\...\.......\MAC_rx.v
.................\...........\.................\...\.......\MAC_top.v
.................\...........\.................\...\.......\MAC_tx.v
.................\...........\.................\...\.......\Phy_int.v
.................\...........\.................\...\.......\reg_int.v
.................\...........\.................\...\.......\RMON.v
.................\...........\.................\...\.......\TECH\CLK_DIV2.v
.................\...........\.................\...\.......\....\CLK_SWITCH.v
.................\...........\.................\...\.......\....\duram.v
.................\...........\.................\...\.......\RMON\RMON_addr_gen.v
.................\...........\.................\...\.......\....\RMON_ctrl.v
.................\...........\.................\...\.......\....\RMON_dpram.v
.................\...........\.................\...\.......\miim\eth_clockgen.v
..........

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