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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 434kb
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  • Author :alf***
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Circuito multiplicador de dos numeros binarios de 4 bits cada uno
Packet file list
(Preview for download)
multip\.lso
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......\....\simulate_dofile.log_back
......\....\work\controlsec.vdb
......\....\....\test1.vdb
......\....\....\top.vdb
......\....\_tmp\ieee\p_0017514958.didat
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......\....\....\....\a_2221974671_0230731466.didat
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......\....\....\....\a_3467682807_3212880686.c
......\....\....\....\a_3467682807_3212880686.didat
......\....\....\....\a_3467682807_3212880686.nt.obj
......\....\....\....\test1_isim_beh.exe_lib.c
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......\....\....\....\test1_isim_beh.exe_lib.nt.obj
......\....\....\....\test1_isim_beh.exe_main.c
......\isim.cmd
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......\......_xdb\cst.xbcd
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......\..........\...\...\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject
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......\..........\...\...\............\.......\Gc_RvReportViewer-Module-Data-top
......\..........\...\...\............\.......\Gc_RvReportViewer-Module-Data-top_StrTbl
......\..........\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default
......\..........\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default_StrTbl
......\..........\...\...\..REGISTRY__\Autonym\regkeys
......\..........\...\...\............\bitgen\regkeys
......\..........\...\...\............\common\regkeys
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......\..........\...\...\............\fuse\regkeys
......\..........\...\...\............\HierarchicalDesign\HDProject\regkeys
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......\..........\...\...\............\hprep6\regk
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