This Verilog HDL Promang

DualPortRAM\DualPortRAM.prj
...........\designer\impl1\ada02592-1.tmp
...........\........\.....\ada02592-3.tmp
...........\........\.....\ada02920-3.tmp
...........\........\.....\ada02920-5.tmp
...........\........\.....\designer.log
...........\........\.....\top.ide_des
...........\........\.....\top.pdb
...........\........\.....\top.pdb.depends
...........\........\.....\top.tcl
...........\........\.....\top_ba.sdf
...........\........\.....\top_ba.v
...........\........\.....\top.adb
...........\........\.....\....dtf\verify.log
...........\........\.....\..._fp\$$FlashPro_08873.L$$
...........\........\.....\......\$$FlashPro_FPBBALTLPT1.L$$
...........\........\.....\......\top.log
...........\........\.....\......\top.pro
...........\........\.....\......\projectData\top.pdb
...........\hdl\send.v
...........\...\top.v
...........\...\writeram.v
...........\...\rec.v
...........\simulation\RAM2k8_R0C0.mem
...........\..........\RAM2k8_R0C1.mem
...........\..........\RAM2k8_R0C2.mem
...........\..........\RAM2k8_R0C3.mem
...........\..........\modelsim.ini.sav
...........\..........\modelsim.ini
...........\.martgen\RAM2k8_work.ixf
...........\........\smartgen.aws
...........\........\RAM2k8\RAM2k8.cxf
...........\........\......\RAM2k8.gen
...........\........\......\RAM2k8.log
...........\........\......\RAM2k8.shx
...........\........\......\RAM2k8.v
...........\........\......\RAM2k8_R0C0.mem
...........\........\......\RAM2k8_R0C1.mem
...........\........\......\RAM2k8_R0C2.mem
...........\........\......\RAM2k8_R0C3.mem
...........\.ynthesis\.recordref
...........\.........\run_options.txt
...........\.........\stdout.log
...........\.........\top.areasrr
...........\.........\top.edn
...........\.........\top.map
...........\.........\top.sdf
...........\.........\top.so
...........\.........\top.srd
...........\.........\top.srm
...........\.........\top.srr
...........\.........\top.tlg
...........\.........\top_sdc.sdc
...........\.........\traplog.tlg
...........\.........\top.srs
...........\.........\top_syn.prj
...........\.........\backup\top.srr
...........\.........\syntmp\top.msg
...........\.........\......\top.plg
...........\viewdraw\viewdraw.ini
...........\........\.f\project.lst
...........\designer\impl1\top_fp\projectData
...........\........\.....\simulation
...........\........\.....\top.dtf
...........\........\.....\top_fp
...........\........\impl1
...........\smartgen\RAM2k8
...........\.ynthesis\backup
...........\.........\coreip
...........\.........\syntmp
...........\viewdraw\sch
...........\........\sym
...........\........\vf
...........\........\wir
...........\component
...........\constraint
...........\coreconsole
...........\designer
...........\hdl
...........\phy_synthesis
...........\simulation
...........\smartgen
...........\stimulus
...........\synthesis
...........\viewdraw
DualPortRAM

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