In this case the function is to achieve a 16-bit multiplier, and to increase the simulation code

db\mux16.asm.qmsg
..\mux16.cbx.xml
..\mux16.cmp.cdb
..\mux16.cmp.hdb
..\mux16.cmp.logdb
..\mux16.cmp.rdb
..\mux16.cmp.tdb
..\mux16.cmp0.ddb
..\mux16.db_info
..\mux16.eco.cdb
..\mux16.eda.qmsg
..\mux16.fit.qmsg
..\mux16.hier_info
..\mux16.hif
..\mux16.map.cdb
..\mux16.map.hdb
..\mux16.map.logdb
..\mux16.map.qmsg
..\mux16.pre_map.cdb
..\mux16.pre_map.hdb
..\mux16.rtlv.hdb
..\mux16.rtlv_sg.cdb
..\mux16.rtlv_sg_swap.cdb
..\mux16.sgdiff.cdb
..\mux16.sgdiff.hdb
..\mux16.signalprobe.cdb
..\mux16.sim.cvwf
..\mux16.sld_design_entry.sci
..\mux16.sld_design_entry_dsc.sci
..\mux16.syn_hier_info
..\mux16.tan.qmsg
..\mux16.tis_db_list.ddb
..\mux16.tmw_info
..\mux16_global_asgn_op.abo
..\prev_cmp_mux16.asm.qmsg
..\prev_cmp_mux16.eda.qmsg
..\prev_cmp_mux16.fit.qmsg
..\prev_cmp_mux16.map.qmsg
..\prev_cmp_mux16.qmsg
..\prev_cmp_mux16.tan.qmsg
..\wed.wsf
incremental_db\README
..............\compiled_partitions\mux16.root_partition.map.kpt
simulation\modelsim\maxii_atoms.v
..........\........\modelsim.ini
..........\........\msim_transcript
..........\........\mux16.sft
..........\........\mux16.vo
..........\........\mux16.vt
..........\........\mux16.vt.bak
..........\........\mux16_modelsim.xrf
..........\........\mux16_run_msim_rtl_verilog.do
..........\........\mux16_run_msim_rtl_verilog.do.bak
..........\........\mux16_run_msim_rtl_verilog.do.bak1
..........\........\mux16_run_msim_rtl_verilog.do.bak10
..........\........\mux16_run_msim_rtl_verilog.do.bak2
..........\........\mux16_run_msim_rtl_verilog.do.bak3
..........\........\mux16_run_msim_rtl_verilog.do.bak4
..........\........\mux16_run_msim_rtl_verilog.do.bak5
..........\........\mux16_run_msim_rtl_verilog.do.bak6
..........\........\mux16_run_msim_rtl_verilog.do.bak7
..........\........\mux16_run_msim_rtl_verilog.do.bak8
..........\........\mux16_run_msim_rtl_verilog.do.bak9
..........\........\mux16_v.sdo
..........\........\vsim.wlf
..........\........\vtf_test.v
..........\........\vtf_test.v.bak
..........\........\rtl_work\_info
..........\........\........\mux16_vlg_tst\verilog.psm
..........\........\........\.............\_primary.dat
..........\........\........\.............\_primary.vhd
..........\........\........\.....\verilog.psm
..........\........\........\.....\_primary.dat
..........\........\........\.....\_primary.vhd
mux16.asm.rpt
mux16.done
mux16.dpf
mux16.eda.rpt
mux16.fit.rpt
mux16.fit.smsg
mux16.fit.summary
mux16.flow.rpt
mux16.map.rpt
mux16.map.smsg
mux16.map.summary
mux16.pin
mux16.pof
mux16.qpf
mux16.qsf
mux16.qws
mux16.sim.rpt
mux16.sof
mux16.tan.rpt
mux16.tan.summary
mux16.v
mux16.v.bak
mux16.vwf
mux16_assignment_defaults.qdf
mux16_nativelink_simulation.rpt
simulation\modelsim\rtl_work\mux16_vlg_tst

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