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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 120kb
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  • Author :vons*****
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Introduction - If you have any usage issues, please Google them yourself
This is a vhdl synthesis of the CORDIC method.
Packet file list
(Preview for download)
Cordic\C-sources
......\.........\genvect.bat
......\.........\gen_testvector.c
......\.........\gen_testvector.exe
......\hdl
......\...\addsub_synthesis.vhd
......\...\atan32_Arch1.vhd
......\...\clockgen_rtl.vhd
......\...\cordic_pkg_pkg.vhd
......\...\cordic_synthesis.vhd
......\...\cordic_tb_struct.vhd
......\...\cordic_tester_behavioral.vhd
......\...\fsm_synthesis.vhd
......\...\shiftn_synthesis.vhd
......\src
......\...\.xrf
......\...\....\addsub_synthesis.xrf
......\...\....\atan32_Arch1.xrf
......\...\....\clockgen_rtl.xrf
......\...\....\cordic_pkg_pkg.xrf
......\...\....\cordic_pkg_pkg_body.xrf
......\...\....\cordic_synthesis.xrf
......\...\....\cordic_tb_struct.xrf
......\...\....\cordic_tester_behavioral.xrf
......\...\....\fsm_synthesis.xrf
......\...\....\shiftn_synthesis.xrf
......\...\addsub
......\...\......\default_view
......\...\......\symbol.sb
......\...\......\synthesis.vhd
......\...\......\synthesis.vhd.info
......\...\......\..................\structure.dh
......\...\atan32
......\...\......\Arch1.vhd
......\...\......\Arch1.vhd.info
......\...\......\..............\structure.dh
......\...\......\default_view
......\...\......\symbol.sb
......\...\clockgen
......\...\........\default_view
......\...\........\rtl.vhd
......\...\........\rtl.vhd.info
......\...\........\............\structure.dh
......\...\........\symbol.sb
......\...\cordic
......\...\......\default_view
......\...\......\symbol.sb
......\...\......\synthesis.bd
......\...\cordic_pkg
......\...\..........\cordic_pkg.info
......\...\..........\...............\structure.dh
......\...\..........\_package.vhd
......\...\..........\_package_body.vhd
......\...\cordic_tb
......\...\.........\default_view
......\...\.........\struct.bd
......\...\.........\symbol.sb
......\...\cordic_tester
......\...\.............\behavioral.vhd
......\...\.............\behavioral.vhd.info
......\...\.............\...................\structure.dh
......\...\.............\...................\testvec.txt
......\...\.............\default_view
......\...\.............\interface
......\...\fsm
......\...\...\default_view
......\...\...\symbol.sb
......\...\...\synthesis.sm
......\...\shiftn
......\...\......\default_view
......\...\......\symbol.sb
......\...\......\synthesis.vhd
......\...\......\synthesis.vhd.info
......\...\......\..................\structure.dh
......\work_mti
......\........\compile.scr
......\........\modelsim.ini
......\........\modelsim.tcl
......\........\tb.do
......\........\tb.scr
......\........\_info
......\work_ps
......\.......\add_files.tcl
Cordic
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