This design is based on the company s ep2s750FPGA altera stopwatch counter chip, which contains six binary counter and decimal counter and 10,000 divider modules.

秒表设计\clkgen.qpf
........\clkgen.qsf
........\db\clkgen.db_info
........\..\clkgen.fit.qmsg
........\..\clkgen.cmp.cdb
........\..\prev_cmp_clkgen.map.qmsg
........\..\prev_cmp_clkgen.qmsg
........\..\clkgen.cbx.xml
........\..\clkgen.hif
........\..\clkgen.asm.qmsg
........\..\clkgen.tan.qmsg
........\..\clkgen.hier_info
........\..\clkgen.map.qmsg
........\..\prev_cmp_clkgen.fit.qmsg
........\..\prev_cmp_clkgen.asm.qmsg
........\..\prev_cmp_clkgen.tan.qmsg
........\..\clkgen.pre_map.cdb
........\..\clkgen.psp
........\..\clkgen.dbp
........\..\clkgen.pss
........\..\clkgen.rtlv_sg_swap.cdb
........\..\clkgen.map_bb.logdb
........\..\clkgen.cmp.ecobp
........\..\clkgen.syn_hier_info
........\..\clkgen.cmp_bb.logdb
........\..\clkgen.sgdiff.cdb
........\..\clkgen.sgdiff.hdb
........\..\clkgen.eco.cdb
........\..\clkgen.map.ecobp
........\..\clkgen.cmp.logdb
........\..\clkgen.asm_labs.ddb
........\..\clkgen.rtlv_sg.cdb
........\..\clkgen.pre_map.hdb
........\..\clkgen.rtlv.hdb
........\..\clkgen.cmp.bpm
........\..\clkgen.sld_design_entry_dsc.sci
........\..\clkgen.map_bb.cdb
........\..\clkgen.map_bb.hdb
........\..\clkgen.sld_design_entry.sci
........\..\clkgen.map.logdb
........\..\clkgen.map.cdb
........\..\clkgen.map.hdb
........\..\clkgen.map.bpm
........\..\clkgen.cmp.tdb
........\..\clkgen.signalprobe.cdb
........\..\clkgen.tis_db_list.ddb
........\..\clkgen.cmp_bb.hdb
........\..\clkgen.cmp_bb.rcf
........\..\clkgen.cmp.hdb
........\..\clkgen.cmp_bb.cdb
........\..\clkgen.cmp.rdb
........\..\clkgen.cmp0.ddb
........\clkgen.map.summary
........\clkgen.pin
........\clkgen.fit.smsg
........\clkgen.fit.summary
........\clkgen.sof
........\clkgen.pof
........\clkgen.tan.summary
........\clkgen.done
........\cnt6.v.bak
........\cnt6.v
........\cnt6.bsf
........\clkgen.bsf
........\clkge.v.bak
........\clkge.v
........\clkgen.vhd.bak
........\clkgen.vhd
........\cnt.vhd.bak
........\cnt.vhd
........\clkgen.map.rpt
........\clkgen.fit.rpt
........\clkgen.asm.rpt
........\clkgen.tan.rpt
........\clkgen.flow.rpt
........\秒表设计1\sec_num.qpf
........\.........\sec_num.qsf
........\.........\db\sec_num.db_info
........\.........\..\sec_num.sld_design_entry.sci
........\.........\..\sec_num.eco.cdb
........\cnt10.bsf
........\clkgen.qws
........\transcript
........\秒表设计1\db
........\db
........\秒表设计1
秒表设计

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．