This is a FPGA-ROM UART' s with practical examples, has completed commissioning

S7_UART
.......\S7_UART
.......\.......\physical
.......\.......\........\.sopc_builder
.......\.......\........\.............\install.ptf
.......\.......\........\db
.......\.......\........\..\altsyncram_lv61.tdf
.......\.......\........\..\uart_if_rom.db_info
.......\.......\........\..\uart_if_rom.eco.cdb
.......\.......\........\..\uart_if_rom.sld_design_entry.sci
.......\.......\........\..\wed.wsf
.......\.......\........\..\wed.zsf
.......\.......\........\div.bsf
.......\.......\........\div.v
.......\.......\........\filter.bsf
.......\.......\........\filter.v
.......\.......\........\rcvr.bsf
.......\.......\........\simulation
.......\.......\........\..........\modelsim
.......\.......\........\..........\........\uart
.......\.......\........\..........\........\....\uart.cr.mti
.......\.......\........\..........\........\....\uart.mpf
.......\.......\........\..........\........\....\work
.......\.......\........\..........\........\....\....\@u@a@r@t_tb
.......\.......\........\..........\........\....\....\...........\verilog.asm
.......\.......\........\..........\........\....\....\...........\_primary.dat
.......\.......\........\..........\........\....\....\...........\_primary.vhd
.......\.......\........\..........\........\....\....\uart
.......\.......\........\..........\........\....\....\....\verilog.asm
.......\.......\........\..........\........\....\....\....\_primary.dat
.......\.......\........\..........\........\....\....\....\_primary.vhd
.......\.......\........\..........\........\....\....\_info
.......\.......\........\sopc_builder_debug_log.txt
.......\.......\........\txmit.bsf
.......\.......\........\uart.bsf
.......\.......\........\uart_if.bsf
.......\.......\........\uart_if.v
.......\.......\........\uart_if_rom.asm.rpt
.......\.......\........\uart_if_rom.bdf
.......\.......\........\uart_if_rom.cdf
.......\.......\........\uart_if_rom.done
.......\.......\........\uart_if_rom.dpf
.......\.......\........\uart_if_rom.eda.rpt
.......\.......\........\uart_if_rom.fit.rpt
.......\.......\........\uart_if_rom.fit.smsg
.......\.......\........\uart_if_rom.fit.summary
.......\.......\........\uart_if_rom.flow.rpt
.......\.......\........\uart_if_rom.map.rpt
.......\.......\........\uart_if_rom.map.summary
.......\.......\........\uart_if_rom.mif
.......\.......\........\uart_if_rom.pin
.......\.......\........\uart_if_rom.pof
.......\.......\........\uart_if_rom.qpf
.......\.......\........\uart_if_rom.qsf
.......\.......\........\uart_if_rom.qws
.......\.......\........\uart_if_rom.sim.rpt
.......\.......\........\uart_if_rom.sof
.......\.......\........\uart_if_rom.tan.rpt
.......\.......\........\uart_if_rom.tan.summary
.......\.......\........\uart_if_rom.v
.......\.......\........\uart_if_rom.vwf
.......\.......\........\uart_if_rom_assignment_defaults.qdf
.......\.......\........\uart_rom.bsf
.......\.......\........\uart_rom.inc
.......\.......\........\uart_rom.mif
.......\.......\........\uart_rom.tdf
.......\.......\........\uart_rom.v
.......\.......\........\uart_rom_bb.v

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