VHDL is used to realize the ADC0809 samples the signal is achieved

AD\db\prev_cmp_vhdl.asm.qmsg
..\..\prev_cmp_vhdl.fit.qmsg
..\..\prev_cmp_vhdl.map.qmsg
..\..\prev_cmp_vhdl.tan.qmsg
..\..\vhdl.asm.qmsg
..\..\vhdl.asm_labs.ddb
..\..\vhdl.cbx.xml
..\..\vhdl.cmp.cdb
..\..\vhdl.cmp.hdb
..\..\vhdl.cmp.kpt
..\..\vhdl.cmp.logdb
..\..\vhdl.cmp.rdb
..\..\vhdl.cmp.tdb
..\..\vhdl.cmp0.ddb
..\..\vhdl.cmp2.ddb
..\..\vhdl.db_info
..\..\vhdl.eco.cdb
..\..\vhdl.fit.qmsg
..\..\vhdl.hier_info
..\..\vhdl.hif
..\..\vhdl.map.cdb
..\..\vhdl.map.hdb
..\..\vhdl.map.logdb
..\..\vhdl.map.qmsg
..\..\vhdl.pre_map.cdb
..\..\vhdl.pre_map.hdb
..\..\vhdl.rpp.qmsg
..\..\vhdl.rtlv.hdb
..\..\vhdl.rtlv_sg.cdb
..\..\vhdl.rtlv_sg_swap.cdb
..\..\vhdl.sgate.rvd
..\..\vhdl.sgate_sm.rvd
..\..\vhdl.sgdiff.cdb
..\..\vhdl.sgdiff.hdb
..\..\vhdl.sld_design_entry.sci
..\..\vhdl.sld_design_entry_dsc.sci
..\..\vhdl.smp_dump.txt
..\..\vhdl.syn_hier_info
..\..\vhdl.tan.qmsg
..\..\vhdl.tis_db_list.ddb
..\..\vhdl.tmw_info
..\incremental_db\compiled_partitions\vhdl.root_partition.map.kpt
..\..............\README
..\UNUSED
..\vhdl.asm.rpt
..\vhdl.done
..\vhdl.fit.rpt
..\vhdl.fit.smsg
..\vhdl.fit.summary
..\vhdl.flow.rpt
..\vhdl.map.rpt
..\vhdl.map.summary
..\vhdl.pin
..\vhdl.pof
..\vhdl.qpf
..\vhdl.qsf
..\vhdl.qws
..\vhdl.sof
..\vhdl.tan.rpt
..\vhdl.tan.summary
..\vhdl.vhd
..\vhdl_assignment_defaults.qdf
..\incremental_db\compiled_partitions
..\db
..\incremental_db
AD

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