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AESverilog

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 86kb
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  • Author :杨***
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Introduction - If you have any usage issues, please Google them yourself
AES encryption algorithm in Verilog Implementation
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(Preview for download)
AES高级加密算法的verilog语言实现\aes_core\bench\CVS\Entries
................................\........\.....\...\Repository
................................\........\.....\...\Root
................................\........\.....\verilog\CVS\Entries
................................\........\.....\.......\...\Repository
................................\........\.....\.......\...\Root
................................\........\.....\.......\test_bench_top.v
................................\........\CVS\Entries
................................\........\...\Repository
................................\........\...\Root
................................\........\doc\aes.pdf
................................\........\...\CVS\Entries
................................\........\...\...\Repository
................................\........\...\...\Root
................................\........\rtl\CVS\Entries
................................\........\...\...\Repository
................................\........\...\...\Root
................................\........\...\verilog\aes_cipher_top.v
................................\........\...\.......\aes_inv_cipher_top.v
................................\........\...\.......\aes_inv_sbox.v
................................\........\...\.......\aes_key_expand_128.v
................................\........\...\.......\aes_rcon.v
................................\........\...\.......\aes_sbox.v
................................\........\...\.......\CVS\Entries
................................\........\...\.......\...\Repository
................................\........\...\.......\...\Root
................................\........\...\.......\timescale.v
................................\........\sim\CVS\Entries
................................\........\...\...\Repository
................................\........\...\...\Root
................................\........\...\rtl_sim\bin\CVS\Entries
................................\........\...\.......\...\...\Repository
................................\........\...\.......\...\...\Root
................................\........\...\.......\...\Makefile
................................\........\...\.......\CVS\Entries
................................\........\...\.......\...\Repository
................................\........\...\.......\...\Root
................................\........\...\.......\run\CVS\Entries
................................\........\...\.......\...\...\Repository
................................\........\...\.......\...\...\Root
................................\........\...\.......\...\waves\CVS\Entries
................................\........\...\.......\...\.....\...\Repository
................................\........\...\.......\...\.....\...\Root
................................\........\...\.......\...\.....\waves.do
................................\........\.yn\bin\comp.dc
................................\........\...\...\CVS\Entries
................................\........\...\...\...\Repository
................................\........\...\...\...\Root
................................\........\...\...\design_spec.dc
................................\........\...\...\lib_spec.dc
................................\........\...\...\read.dc
................................\........\...\CVS\Entries
................................\........\...\...\Repository
................................\........\...\...\Root
................................\........\vim_session.vim
................................\........\sim\rtl_sim\run\waves\CVS
................................\........\...\.......\bin\CVS
................................\........\...\.......\run\CVS
................................\........\...\.......\...\waves
................................\........\bench\verilog\CVS
................................\........\rtl\verilog\CVS
................................\........\sim\rtl_sim\bin
................................\........\...\.......\CVS
................................\........\...\.......\run
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