This achieved in DE0 board D5M+ VGA images with real-time display program, complete project

DE0_D5M\DE0_D5M.pin
.......\DE0_D5M.qpf
.......\DE0_D5M.qsf
.......\DE0_D5M.sof
.......\DE0_D5M.v
.......\incremental_db\compiled_partitions\DE0_D5M.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.atm
.......\..............\...................\DE0_D5M.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.hdbx
.......\..............\...................\DE0_D5M.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.kpt
.......\..............\...................\DE0_D5M.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.logdb
.......\..............\...................\DE0_D5M.root_partition.cmp.atm
.......\..............\...................\DE0_D5M.root_partition.cmp.dfp
.......\..............\...................\DE0_D5M.root_partition.cmp.hdbx
.......\..............\...................\DE0_D5M.root_partition.cmp.kpt
.......\..............\...................\DE0_D5M.root_partition.cmp.logdb
.......\..............\...................\DE0_D5M.root_partition.cmp.rcf
.......\..............\...................\DE0_D5M.root_partition.map.atm
.......\..............\...................\DE0_D5M.root_partition.map.dpi
.......\..............\...................\DE0_D5M.root_partition.map.hdbx
.......\..............\...................\DE0_D5M.root_partition.map.kpt
.......\..............\...................\DE0_D5M.root_partition.merge_hb.atm
.......\..............\...................\DE0_D5M.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.atm
.......\..............\...................\DE0_D5M.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.dpi
.......\..............\...................\DE0_D5M.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.hdbx
.......\..............\...................\DE0_D5M.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.kpt
.......\..............\...................\DE0_D5M.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.logdb
.......\..............\compiled_partitions
.......\..............\README
.......\incremental_db
.......\Sdram_Control_4Port\command.v
.......\...................\control_interface.v
.......\...................\Sdram_Control_4Port.v
.......\...................\Sdram_FIFO.v
.......\...................\Sdram_Params.h
.......\...................\sdr_data_path.v
.......\Sdram_Control_4Port
.......\V\CCD_Capture.v
.......\.\CCD_Capture.v.bak
.......\.\debounce.vhd
.......\.\I2C_CCD_Config.v
.......\.\I2C_CCD_Config.v.bak
.......\.\I2C_Controller.v
.......\.\Line_Buffer.v
.......\.\RAW2RGB.v
.......\.\Reset_Delay.v
.......\.\Reset_Delay.v.bak
.......\.\sdram_pll.bsf
.......\.\sdram_pll.ppf
.......\.\sdram_pll.qip
.......\.\sdram_pll.v
.......\.\sdram_pll_wave0.jpg
.......\.\sdram_pll_waveforms.html
.......\.\VGA_Controller.v
.......\.\VGA_Controller.v.bak
.......\.\VGA_Param.h
.......\V
DE0_D5M

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