Verilog a simple drawing tools, tools, electrical connections to the database information into the program information through the database to refresh the screen, and exported to the user modeling verilog gate-level statement

Verilog Helper源代码\Debug\FalDlg.obj
....................\.....\FinDlg.obj
....................\.....\LineDlg.obj
....................\.....\MainFrm.obj
....................\.....\msado15.tlh
....................\.....\msado15.tli
....................\.....\my_data1.udl
....................\.....\NorDlg.obj
....................\.....\RESULTDLG.obj
....................\.....\StaDlg.obj
....................\.....\StdAfx.obj
....................\.....\vc60.idb
....................\.....\vc60.pdb
....................\.....\正式.exe
....................\.....\正式.ilk
....................\.....\正式.obj
....................\.....\正式.pch
....................\.....\正式.pdb
....................\.....\正式.res
....................\.....\正式Doc.obj
....................\.....\正式View.obj
....................\FalDlg.cpp
....................\FalDlg.h
....................\FinDlg.cpp
....................\FinDlg.h
....................\LineDlg.cpp
....................\LineDlg.h
....................\MainFrm.cpp
....................\MainFrm.h
....................\msado15.tlh
....................\msado15.tli
....................\my_data1.udl
....................\NorDlg.cpp
....................\NorDlg.h
....................\ReadMe.txt
....................\res\b.bmp
....................\...\Toolbar.bmp
....................\...\正式.ico
....................\...\正式.rc2
....................\...\正式Doc.ico
....................\resource.h
....................\RESULTDLG.cpp
....................\RESULTDLG.h
....................\StaDlg.cpp
....................\StaDlg.h
....................\StdAfx.cpp
....................\StdAfx.h
....................\正式.aps
....................\正式.clw
....................\正式.cpp
....................\正式.dsp
....................\正式.dsw
....................\正式.h
....................\正式.ncb
....................\正式.opt
....................\正式.plg
....................\正式.rc
....................\正式Doc.cpp
....................\正式Doc.h
....................\正式View.cpp
....................\正式View.h
....................\比赛数据库5.mdb
....................\Debug
....................\res
Verilog Helper源代码

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