DCT / VHDL Discrete Cosine Transform

DCT\dct_top.vhd
...\dct.vhd
...\dctpack.vhd
...\read_address.vhd
...\transpose.vhd
...\dctorg
...\......\work
...\......\....\_info
...\......\....\dctpack
...\......\....\.......\_primary.dat
...\......\....\.......\_vhdl.asm
...\......\....\.......\body.dat
...\......\....\.......\body.asm
...\......\....\read_address
...\......\....\............\_primary.dat
...\......\....\............\read_address_arch.dat
...\......\....\............\read_address_arch.asm
...\......\....\write_address
...\......\....\.............\_primary.dat
...\......\....\.............\write_address_arch.dat
...\......\....\.............\write_address_arch.asm
...\......\....\transpose
...\......\....\.........\_primary.dat
...\......\....\.........\transpose_arch.dat
...\......\....\.........\transpose_arch.asm
...\......\....\dct
...\......\....\...\_primary.dat
...\......\....\...\dct_arch.dat
...\......\....\...\dct_arch.asm
...\......\....\dct_top_pkg
...\......\....\...........\_primary.dat
...\......\....\...........\_vhdl.asm
...\......\....\dct_top
...\......\....\.......\_primary.dat
...\......\....\.......\dct_top_arch.dat
...\......\....\.......\dct_top_arch.asm
...\......\....\dct_tb
...\......\....\......\_primary.dat
...\......\....\......\struct.dat
...\......\....\......\struct.asm
...\......\....\dct_tester
...\......\....\..........\_primary.dat
...\......\....\..........\spec.dat
...\......\....\..........\spec.asm
...\......\....\ch_sram
...\......\....\.......\_primary.dat
...\......\....\.......\sram_arch.dat
...\......\....\.......\sram_arch.asm
...\......\....\cfg_ch_sram_arch
...\......\....\................\_primary.dat
...\......\....\................\_vhdl.asm
...\......\....\sram
...\......\....\....\_primary.dat
...\......\....\....\sram_arch.dat
...\......\....\....\sram_arch.asm
...\......\....\cfg_sram_arch
...\......\....\.............\_primary.dat
...\......\....\.............\_vhdl.asm
...\......\....\tb_ch_sram
...\......\....\..........\_primary.dat
...\......\....\..........\structure.dat
...\......\....\..........\structure.asm
...\......\....\cfg_tb_ch_sram_structure
...\......\....\........................\_primary.dat
...\......\....\........................\_vhdl.asm
...\......\....\tb_sram
...\......\....\.......\_primary.dat
...\......\....\.......\structure.dat
...\......\....\.......\structure.asm
...\......\....\cfg_tb_sram_structure
...\......\....\.....................\_primary.dat
...\......\....\.....................\_vhdl.asm
...\......\dcttest.mpf
...\......\write_address.vhd
...\......\dct_top.vhd
...\......\dctpack.vhd
...\......\read_address.vhd
...\......\transpose.vhd
...\......\dct.vhd
...\......\dct_tester.vhd
...\......\dct_tb.vhd
...\......\barbara_left.dat
...\......\barbara_right.dat
...\......\dct_tb.vhd.bak
...\......\tb_sram.vhd
...\......\sram.vhd
...\......\tb_ch_sram.vhd
...\......\ch_sram.vhd
...\......\dct.vhd.bak
...\......\ch_sram.vhd.bak
...\......\dct_tester.vhd.bak
...\......\tb_ch_sram.vhd.bak
...\......\mem_init_right.txt
...\......\barbara_right.txt
...\......\convert_to_fpga.txt
...\......\fpga_to_text.txt
...\......\mem_init_left.txt
...\......\barbara_left.txt
...\......\mem_init_right.dat
...\......\barbara_left.dat.bak

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