Complete the shift register using Verilog HDL hardware implementation, is very practical.

exp5\cmp_state.ini
....\db\exp5.asm.qmsg
....\..\exp5.cbx.xml
....\..\exp5.cmp.cdb
....\..\exp5.cmp.hdb
....\..\exp5.cmp.rdb
....\..\exp5.cmp.tdb
....\..\exp5.cmp0.ddb
....\..\exp5.db_info
....\..\exp5.eco.cdb
....\..\exp5.eds_overflow
....\..\exp5.fit.qmsg
....\..\exp5.hier_info
....\..\exp5.hif
....\..\exp5.map.cdb
....\..\exp5.map.hdb
....\..\exp5.map.qmsg
....\..\exp5.pre_map.cdb
....\..\exp5.pre_map.hdb
....\..\exp5.psp
....\..\exp5.rtlv.hdb
....\..\exp5.rtlv_sg.cdb
....\..\exp5.rtlv_sg_swap.cdb
....\..\exp5.sgdiff.cdb
....\..\exp5.sgdiff.hdb
....\..\exp5.signalprobe.cdb
....\..\exp5.sim.hdb
....\..\exp5.sim.qmsg
....\..\exp5.sim.rdb
....\..\exp5.sld_design_entry.sci
....\..\exp5.sld_design_entry_dsc.sci
....\..\exp5.syn_hier_info
....\..\exp5.tan.qmsg
....\..\exp5_cmp.qrpt
....\..\exp5_sim.qrpt
....\exp5.asm.rpt
....\exp5.done
....\exp5.fit.eqn
....\exp5.fit.rpt
....\exp5.fit.summary
....\exp5.flow.rpt
....\exp5.map.eqn
....\exp5.map.rpt
....\exp5.map.summary
....\exp5.pin
....\exp5.pof
....\exp5.qpf
....\exp5.qsf
....\exp5.qws
....\exp5.sim.rpt
....\exp5.sof
....\exp5.tan.rpt
....\exp5.tan.summary
....\exp5.v
....\exp5.vwf
....\exp5_1.pof
....\db
exp5

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