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SPI_Bridge_Design_Example

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 276kb
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  • Author :米***
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Introduction - If you have any usage issues, please Google them yourself
Based on ALTERA' s nios2 the SPI communication, the document contains the entire project, including master-slave mode, a good reference.
Packet file list
(Preview for download)
SPI_Bridge_Design_Example\readme.txt
.........................\spi_bridge_3c120\.metadata\.lock
.........................\................\.........\.log
.........................\................\.........\.mylyn\repositories.xml.zip
.........................\................\.........\.plugins\org.eclipse.cdt.core\.log
.........................\................\.........\........\.............ore.resources\.root\.indexes\history.version
.........................\................\.........\........\..........................\.....\........\properties.version
.........................\................\.........\........\..........................\.....\1.tree
.........................\................\.........\........\..........................\.safetable\org.eclipse.core.resources
.........................\................\.........\........\..................untime\.settings\org.eclipse.cdt.ui.prefs
.........................\................\.........\........\........................\.........\org.eclipse.core.resources.prefs
.........................\................\.........\........\........................\.........\org.eclipse.epp.usagedata.recording.prefs
.........................\................\.........\........\........................\.........\org.eclipse.equinox.p2.ui.sdk.prefs
.........................\................\.........\........\........................\.........\org.eclipse.mylyn.context.core.prefs
.........................\................\.........\........\........................\.........\org.eclipse.team.cvs.ui.prefs
.........................\................\.........\........\........................\.........\org.eclipse.team.ui.prefs
.........................\................\.........\........\........................\.........\org.eclipse.ui.ide.prefs
.........................\................\.........\........\........................\.........\org.eclipse.ui.prefs
.........................\................\.........\........\........................\.........\org.eclipse.ui.workbench.prefs
.........................\................\.........\........\............epp.usagedata.recording\upload0.csv
.........................\................\.........\........\...................................\upload1.csv
.........................\................\.........\........\...................................\upload2.csv
.........................\................\.........\........\...................................\upload3.csv
.........................\................\.........\........\...................................\usagedata.csv
.........................\................\.........\........\............ui.workbench\dialog_settings.xml
.........................\................\.........\........\........................\workbench.xml
.........................\................\.........\........\........................\workingsets.xml
.........................\................\.........\version.ini
.........................\................\.sopc_builder\filters.xml
.........................\................\.............\preferences.xml
.........................\................\cpu_spi_core.bsf
.........................\................\cpu_spi_core.sopc
.........................\................\cpu_spi_core.sopcinfo
.........................\................\cpu_spi_core.v
.........................\................\db\spi_bridge.db_info
.........................\................\..\spi_bridge.eco.cdb
.........................\................\..\spi_bridge.sld_design_entry.sci
.........................\................\incremental_db\README
.........................\................\pll.bsf
.........................\................\pll.qip
.........................\................\pll.v
.........................\................\software_examples\app\spi_bridge_test\alt_spi_to_avalon_bridge\byte_to_core.c
.........................\................\.................\...\...............\........................\byte_to_core.h
.........................\................\..
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