Synchronous series and the conversion process, a serial input, 8-bit parallel output.

change\automake.log
......\change.cmd_log
......\change.dhp
......\change.ise
......\change.ise_ISE_Backup
......\change.lso
......\change.ngc
......\change.ngr
......\change.prj
......\change.stx
......\change.syr
......\change.v
......\change_summary.html
......\change_vhdl.prj
......\test.v
......\test_v.fdo
......\test_v.udo
......\transcript
......\vsim.wlf
......\work\change\verilog.asm
......\....\......\_primary.dat
......\....\......\_primary.vhd
......\....\glbl\verilog.asm
......\....\....\_primary.dat
......\....\....\_primary.vhd
......\....\test_v\verilog.asm
......\....\......\_primary.dat
......\....\......\_primary.vhd
......\....\_info
......\xst\work\hdllib.ref
......\...\....\vlg6A\change.bin
......\__projnav\change.gfl
......\.........\change.xst
......\.........\change_flowplus.gfl
......\.........\createTF.err
......\.........\runXst_tcl.rsp
......\.........\sumrpt_tcl.rsp
......\__projnav.log
......\xst\dump.xst\change.prj\ngx\notopt
......\...\........\..........\...\opt
......\...\........\..........\ngx
......\...\........\change.prj
......\...\work\vlg6A
......\work\change
......\....\glbl
......\....\test_v
......\xst\dump.xst
......\...\work
......\work
......\xst
......\_xmsgs
......\__projnav
change
......\.untf
......\bitgen.ut
......\change.bgn
......\change.bit
......\change.bld
......\change.drc
......\change.mrp
......\change.nc1
......\change.ncd
......\change.ngd
......\change.ngm
......\change.pad
......\change.pad_txt
......\change.par
......\change.pcf
......\change.placed_ncd_tracker
......\change.routed_ncd_tracker
......\change.twr
......\change.twx
......\change.ut
......\change.xpi
......\change_map.ncd
......\change_map.ngm
......\change_pad.csv
......\change_pad.txt
......\_ngo\netlist.lst
......\._projnav\bitgen.rsp
......\.........\change_ncdTOut_tcl.rsp
......\.........\ednTOngd_tcl.rsp
......\.........\nc1TOncd_tcl.rsp
......\_ngo

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