verilog，fpga easy030，led

LED\designer\impl1\ada03412-1.tmp
...\........\.....\designer.log
...\........\.....\designer_synth_check.log
...\........\.....\LED.adb
...\........\.....\....dtf\verify.log
...\........\.....\LED.ide_des
...\........\.....\LED.lok
...\........\.....\LED.pdb
...\........\.....\LED.pdb.depends
...\........\.....\LED.tcl
...\........\.....\LED_ba.sdf
...\........\.....\LED_ba.v
...\........\.....\....fp\$$FlashPro_FPBBALTLPT1.L$$
...\........\.....\......\LED.log
...\........\.....\......\LED.pro
...\........\.....\......\projectData\LED.pdb
...\hdl\LED.v
...\LED.prj
...\simulation\modelsim.ini
...\..........\modelsim.ini.sav
...\..........\modelsim.log
...\..........\postsynth\@l@e@d\verilog.psm
...\..........\.........\......\_primary.dat
...\..........\.........\......\_primary.dbs
...\..........\.........\......\_primary.vhd
...\..........\.........\testbench\verilog.psm
...\..........\.........\.........\_primary.dat
...\..........\.........\.........\_primary.dbs
...\..........\.........\.........\_primary.vhd
...\..........\.........\_info
...\..........\.........\_vmake
...\..........\.resynth\@l@e@d\verilog.psm
...\..........\........\......\_primary.dat
...\..........\........\......\_primary.dbs
...\..........\........\......\_primary.vhd
...\..........\........\testbench\verilog.psm
...\..........\........\.........\_primary.dat
...\..........\........\.........\_primary.dbs
...\..........\........\.........\_primary.vhd
...\..........\........\_info
...\..........\........\_vmake
...\..........\run.do
...\..........\vsim.wlf
...\.martgen\smartgen.aws
...\.timulus\testbench.v
...\.ynthesis\backup\LED.srr
...\.........\LED.areasrr
...\.........\LED.edn
...\.........\LED.map
...\.........\LED.pdc
...\.........\LED.sdf
...\.........\LED.so
...\.........\LED.srd
...\.........\LED.srm
...\.........\LED.srr
...\.........\LED.srs
...\.........\LED.szr
...\.........\LED.tlg
...\.........\LED.v
...\.........\LED_sdc.sdc
...\.........\LED_syn.prj
...\.........\run_options.txt
...\.........\stdout.log
...\.........\.yntmp\LED.plg
...\viewdraw\vf\project.lst
...\........\viewdraw.ini
...\designer\impl1\LED_fp\projectData
...\........\.....\LED.dtf
...\........\.....\LED_fp
...\........\.....\simulation
...\simulation\postsynth\@l@e@d
...\..........\.........\testbench
...\..........\.........\_temp
...\..........\.resynth\@l@e@d
...\..........\........\testbench
...\..........\........\_temp
...\designer\impl1
...\simulation\postsynth
...\..........\presynth
...\.ynthesis\backup
...\.........\coreip
...\.........\syntmp
...\viewdraw\sch
...\........\sym
...\........\vf
...\........\wir
...\component
...\constraint
...\coreconsole
...\designer
...\hdl
...\phy_synthesis
...\simulation
...\smartgen
...\stimulus
...\synthesis
...\viewdraw
LED

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