The main objective of the project is to reduce the complexity of the digital circuit with improvement in performance. Two versions of a reconfi gurable logic element are implemented one without extra embedded registration and the other with extra embedded registration. The one with extra embedded registration requires an additional latch but reduces the computing time considerably. Both these versions can be configured as any one of the 27 fundamental NCL gates, including the resettable and inverting variations. The two approaches are compared with each other showing that the version with extra embedded registration requires less computing time than the version without extra embedded registration.

with er full.txt
without er full.txt
LUT CODING.txt

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