TWO PORT RAM Mactel' s detailed user guide, through specific examples to explain the particularly clear, for use actel fpga chip company is very helpful!

Two_port_RAM\smartgen\two_portRAM\two_portRAM.gen
............\........\...........\two_portRAM.log
............\........\...........\two_portRAM.shx
............\........\...........\two_portRAM_R0C0.mem
............\........\...........\two_portRAM.cxf
............\........\...........\two_portRAM.v
............\........\two_portRAM_work.ixf
............\........\smartgen.aws
............\hdl\Wr_Re_ctrl.v
............\...\top.v
............\...\hdlsynchk.tcl
............\viewdraw\vf\project.lst
............\........\viewdraw.ini
............\simulation\run.do
............\..........\modelsim.log
............\..........\postsynth\_info
............\..........\.........\read_wirte_ram\_primary.vhd
............\..........\.........\..............\verilog.psm
............\..........\.........\..............\_primary.dat
............\..........\.........\two_port@r@a@m\_primary.vhd
............\..........\.........\..............\verilog.psm
............\..........\.........\..............\_primary.dat
............\..........\.........\.op\_primary.vhd
............\..........\.........\...\verilog.psm
............\..........\.........\...\_primary.dat
............\..........\.........\stimulus\_primary.vhd
............\..........\.........\........\verilog.psm
............\..........\.........\........\_primary.dat
............\..........\.........\tb_clock_minmax\_primary.vhd
............\..........\.........\...............\verilog.psm
............\..........\.........\...............\_primary.dat
............\..........\.........\.estbench\_primary.vhd
............\..........\.........\.........\verilog.psm
............\..........\.........\.........\_primary.dat
............\..........\vsim.wlf
............\..........\presynth\_info
............\..........\........\two_port@r@a@m\_primary.vhd
............\..........\........\..............\verilog.psm
............\..........\........\..............\_primary.dat
............\..........\........\read_wirte_ram\_primary.vhd
............\..........\........\..............\verilog.psm
............\..........\........\..............\_primary.dat
............\..........\........\top\_primary.vhd
............\..........\........\...\verilog.psm
............\..........\........\...\_primary.dat
............\..........\........\stimulus\_primary.vhd
............\..........\........\........\verilog.psm
............\..........\........\........\_primary.dat
............\..........\........\tb_clock_minmax\_primary.vhd
............\..........\........\...............\verilog.psm
............\..........\........\...............\_primary.dat
............\..........\........\.estbench\_primary.vhd
............\..........\........\.........\verilog.psm
............\..........\........\.........\_primary.dat
............\..........\modelsim.ini.sav
............\..........\meminit.dat
............\..........\two_portRAM_R0C0.mem
............\..........\modelsim.ini
............\.ynthesis\stdout.log
............\.........\.yntmp\top_flink.htm
............\.........\......\top_srr.htm
............\.........\......\top_toc.htm
............\.........\......\sap.log
............\.........\......\top.plg
............\.........\......\top.msg
............\.........\top.srr
............\.........\top.htm
............\.........\top.tlg
............\.........\top.fse
............\.........\traplog.tlg
............\.........\.recordref
............\.........\top.srd
............\.........\top.srm
............\.........\top.map
............\.........\top.edn
............\.........\top.sdf
............\.........\top_sdc.sdc
............\.........\top.areasrr
............\.........\top_drc.rpt
............\.........\top_syn.prd
............\.........\top.v
............\.........\top.srs
............\.........\top.sap
............\.........\top_syn.prj
............\.timulus\top.hpj
............\........\waveperl.log
............\........\BtimErrors.log
............\........\files_to_build.txt
............\........\top_tbench.btim
............\........\top.dsk
............\........\top_tbench.v
........

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