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Flintstone

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 6kb
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  • Author :jimm*****
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Introduction - If you have any usage issues, please Google them yourself
The Flintstones State Machine operates as follows: 1. The State Machine has two states, State Bed and State Rock. 2. There is one output, Fred, which takes the value 0 in State Bed and 1 in State Rock. 3. A reset, caused by a low level on Reset_n, puts the State Machine into State Bed. 4. The State Machine waits in State Bed while Barney is low, and enters State Rock when Barney goes high. 5. The State Machine then waits in State Rock while Wilma is low, and returns to State Bed when Wilma goes high.
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Flintstone.doc
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