Verilog FPGA

liushuideng_v\db\liushuideng.asm.qmsg
.............\..\liushuideng.asm_labs.ddb
.............\..\liushuideng.cbx.xml
.............\..\liushuideng.cmp.cdb
.............\..\liushuideng.cmp.hdb
.............\..\liushuideng.cmp.kpt
.............\..\liushuideng.cmp.logdb
.............\..\liushuideng.cmp.rdb
.............\..\liushuideng.cmp.tdb
.............\..\liushuideng.cmp0.ddb
.............\..\liushuideng.cmp2.ddb
.............\..\liushuideng.dbp
.............\..\liushuideng.db_info
.............\..\liushuideng.eco.cdb
.............\..\liushuideng.fit.qmsg
.............\..\liushuideng.hier_info
.............\..\liushuideng.hif
.............\..\liushuideng.map.cdb
.............\..\liushuideng.map.hdb
.............\..\liushuideng.map.logdb
.............\..\liushuideng.map.qmsg
.............\..\liushuideng.pre_map.cdb
.............\..\liushuideng.pre_map.hdb
.............\..\liushuideng.psp
.............\..\liushuideng.rtlv.hdb
.............\..\liushuideng.rtlv_sg.cdb
.............\..\liushuideng.rtlv_sg_swap.cdb
.............\..\liushuideng.sgdiff.cdb
.............\..\liushuideng.sgdiff.hdb
.............\..\liushuideng.signalprobe.cdb
.............\..\liushuideng.sld_design_entry.sci
.............\..\liushuideng.sld_design_entry_dsc.sci
.............\..\liushuideng.syn_hier_info
.............\..\liushuideng.tan.qmsg
.............\liushuideng.asm.rpt
.............\liushuideng.done
.............\liushuideng.fit.rpt
.............\liushuideng.fit.smsg
.............\liushuideng.fit.summary
.............\liushuideng.flow.rpt
.............\liushuideng.map.rpt
.............\liushuideng.map.summary
.............\liushuideng.pin
.............\liushuideng.pof
.............\liushuideng.qpf
.............\liushuideng.qsf
.............\liushuideng.qws
.............\liushuideng.sof
.............\liushuideng.tan.rpt
.............\liushuideng.tan.summary
.............\liushuideng.v
.............\db
liushuideng_v

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