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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 52kb
  • Downloaded :0次
  • Author :wangz******
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
16 Lantern 4 beat loop points, according to a certain order of loop
Packet file list
(Preview for download)
caideng\Block1.bdf
.......\caideng.bsf
.......\caideng.done
.......\caideng.flow.rpt
.......\caideng.map.eqn
.......\caideng.map.rpt
.......\caideng.map.summary
.......\caideng.qpf
.......\caideng.qsf
.......\caideng.qws
.......\caideng.v
.......\db\caideng.cbx.xml
.......\..\caideng.cmp.qrpt
.......\..\caideng.cmp.rdb
.......\..\caideng.dbp
.......\..\caideng.db_info
.......\..\caideng.eco.cdb
.......\..\caideng.hier_info
.......\..\caideng.hif
.......\..\caideng.map.cdb
.......\..\caideng.map.hdb
.......\..\caideng.map.qmsg
.......\..\caideng.pre_map.cdb
.......\..\caideng.pre_map.hdb
.......\..\caideng.psp
.......\..\caideng.rtlv.hdb
.......\..\caideng.rtlv_sg.cdb
.......\..\caideng.rtlv_sg_swap.cdb
.......\..\caideng.sgdiff.cdb
.......\..\caideng.sgdiff.hdb
.......\..\caideng.sld_design_entry.sci
.......\..\caideng.sld_design_entry_dsc.sci
.......\..\caideng.syn_hier_info
.......\db
caideng
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