Which contains information on the stepper motor and controlled by FPGA Verilog HDL sequencing, and the c sequence.

步进电机C\bjdj
.........\bjdj.c
.........\bjdj.hex
.........\bjdj.LST
.........\bjdj.M51
.........\bjdj.OBJ
.........\bjdj.Opt
.........\bjdj.plg
.........\bjdj.Uv2
.........\bjdj_Opt.Bak
.........\bjdj_Uv2.Bak
.........\TEMP.LST
.........\WAVE.LIN
.........\步进电机
.........\步进电机.BIN
.........\步进电机.LST
.........\步进电机.M51
........资料\4线步进电机时序精析.doc
............\FPGA在步进电机控制中的应用.doc
............\MP28GA步进电机+ULN2003APG驱动相关资料.doc
............\《IC课程设计》报告模版.doc
............\单片机控制步进电机驱动器工作原理.doc
............\基于FPGA产生随机数的方法.doc
............\基于FPGA控制的步进电机驱动设计.doc
............\步进电机原理说明.doc
............\步进电机参数.jpg
............\步进电机图.jpg
............\步进电机工作原理.doc
............\步进电机技术要求.jpg
............\步进电机驱动原理图.pdf
machine_control_design\.lso
......................\control_design.bgn
......................\control_design.bit
......................\control_design.bld
......................\control_design.cel
......................\control_design.cmd_log
......................\control_design.drc
......................\control_design.lfp
......................\control_design.lso
......................\control_design.ncd
......................\control_design.ngc
......................\control_design.ngd
......................\control_design.ngr
......................\control_design.pad
......................\control_design.par
......................\control_design.pcf
......................\control_design.prj
......................\control_design.stx
......................\control_design.syr
......................\control_design.twr
......................\control_design.twx
......................\control_design.ucf
......................\control_design.unroutes
......................\control_design.ut
......................\control_design.v
......................\control_design.xpi
......................\control_design.xst
......................\control_design_fpga_editor.log
......................\control_design_guide.ncd
......................\control_design_map.map
......................\control_design_map.mrp
......................\control_design_map.ncd
......................\control_design_map.ngm
......................\control_design_pad.csv
......................\control_design_pad.txt
......................\control_design_prev_built.ngd
......................\control_design_summary.html
......................\control_design_summary.xml
......................\control_design_usage.xml
......................\data_input.v
......................\device_usage_statistics.html
......................\lcd_display.v
......................\machine_control_design.ise
......................\machine_control_design.ise_ISE_Backup
......................\machine_control_design.ntrc_log
......................\machine_ctl.v
......................\netgen\synthesis\control_design_synthesis.nlf
......................\......\.........\control_design_synthesis.v
......................\timing.twr
......................\xst\dump.xst\control_design.prj\ntrc.scr
......................\...\work\hdllib.ref
......................\...\....\vlg06\control__design.bin
......................\...\....\...50\lcd__display.bin
......................\...\....\....F\machine__ctl.bin
......................\...\....\...69\data__input.bin
......................\_impact.cmd
......................\_impact.log
......................\.ngo\netlist.lst
......................\_pace.ucf
......................\.xmsgs\bitgen.xmsgs
......................\......\map.xmsgs
......................\......\netgen.xmsgs
......................\......\ngdbuild.xmsgs
......................\......\par.xmsgs
......................\......\trce.xmsgs
......................\......\xst.xmsgs
......................\xst\dump.xst\control_design.prj\ngx\notopt
......................\...\........\..................\...\opt
......................\...\........\..................\ngx
......................\...\........\control_design.prj

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