SDRAM read and write Verilog source code control testing procedures.

sdram_hr_hw\sdram_hr_hw\SDRAM_HR_HW.asm.rpt
...........\...........\SDRAM_HR_HW.done
...........\...........\SDRAM_HR_HW.dpf
...........\...........\SDRAM_HR_HW.fit.rpt
...........\...........\SDRAM_HR_HW.fit.smsg
...........\...........\SDRAM_HR_HW.fit.summary
...........\...........\SDRAM_HR_HW.flow.rpt
...........\...........\SDRAM_HR_HW.map.rpt
...........\...........\SDRAM_HR_HW.map.smsg
...........\...........\SDRAM_HR_HW.map.summary
...........\...........\SDRAM_HR_HW.pin
...........\...........\SDRAM_HR_HW.pof
...........\...........\SDRAM_HR_HW.qpf
...........\...........\SDRAM_HR_HW.qsf
...........\...........\SDRAM_HR_HW.qsf.bak
...........\...........\SDRAM_HR_HW.sof
...........\...........\SDRAM_HR_HW.tan.rpt
...........\...........\SDRAM_HR_HW.tan.summary
...........\...........\SDRAM_HR_HW.v
...........\...........\.EG7_LUT\SEG7_LUT.v
...........\...........\........\SEG7_LUT_8.v
...........\...........\.dram_Control_2Port\command.v
...........\...........\...................\control_interface.v
...........\...........\...................\Sdram_Controller.v
...........\...........\...................\Sdram_Params.h
...........\...........\...................\Sdram_PLL.v
...........\...........\...................\sdr_data_path.v
...........\...........\...................\transcript
...........\...........\db\SDRAM_HR_HW.db_info
...........\...........\SEG7_LUT
...........\...........\Sdram_Control_2Port
...........\...........\db
...........\sdram_hr_hw
sdram_hr_hw

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