xilinx spartan2 fpgaddr2 control code, using verilog preparation, can be integrated

ddr2_sdram\par\create_ise.bat
..........\...\icon_coregen.xco
..........\...\ila_coregen.xco
..........\...\ise_run.txt
..........\...\mem_interface_top.ut
..........\...\mem_interface_top_sp3a.ut
..........\...\readme.txt
..........\...\rem_files_syn_lin.bat
..........\...\rem_files_syn_win.bat
..........\...\rem_files_xst_lin.bat
..........\...\rem_files_xst_win.bat
..........\...\set_ise_prop.tcl
..........\...\set_ise_prop_sp3a.tcl
..........\...\synplicity.bat
..........\...\vio_coregen.xco
..........\...\xst.bat
..........\sim\ddr2_model.v
..........\...\ddr2_model_custom_parameters.vh
..........\...\ddr2_model_parameters.vh
..........\...\glbl.v
..........\...\hyb18t512xx0b2f_0129.v
..........\...\hyb18t512xx0b2f_0129_custom.v
..........\...\hyx18t1gxx0c2x.v
..........\...\hyx18t1gxx0c2x_custom.v
..........\...\qimonda_package.vhd
..........\...\qimonda_package_custom.vhd
..........\...\set_hold.vh
..........\...\sim.do
..........\...\sim_tb_top.v
..........\...\sim_tb_top.vhd
..........\...\sim_tb_top_qimonda.v
..........\...\sim_tb_top_qimonda.vhd
..........\...\wiredly.v
..........\...\wiredly.vhd
..........\.ynth\mem_interface_top_synp.sdc
..........\.....\script_synp.tcl
..........\verilog\dcm.txt
..........\.......\dinfo.xml
..........\.......\dsigs.xml
..........\.......\filenames.xml
..........\.......\hw_details.txt
..........\.......\nodcm.txt
..........\.......\rtl\addr_gen.v
..........\.......\...\cal_ctl.v
..........\.......\...\cal_top.v
..........\.......\...\clk_dcm.v
..........\.......\...\cmd_fsm.v
..........\.......\...\cmp_data.v
..........\.......\...\controller.v
..........\.......\...\controller_iobs.v
..........\.......\...\data_gen.v
..........\.......\...\data_path.v
..........\.......\...\data_path_iobs.v
..........\.......\...\data_read.v
..........\.......\...\data_read_controller.v
..........\.......\...\data_write.v
..........\.......\...\dcm_constraints.sdc
..........\.......\...\dqs_delay.v
..........\.......\...\fifo_0_wr_en.v
..........\.......\...\fifo_1_wr_en.v
..........\.......\...\infrastructure.v
..........\.......\...\infrastructure_iobs.v
..........\.......\...\infrastructure_top.v
..........\.......\...\infrastructure_top0.v
..........\.......\...\iobs.v
..........\.......\...\main.v
..........\.......\...\mem_interface_top.v
..........\.......\...\mem_interface_top_nodcm.v
..........\.......\...\parameters.v
..........\.......\...\ram8d.v
..........\.......\...\rd_gray_cntr.v
..........\.......\...\s3_dm_iob.v
..........\.......\...\s3_dqs_iob.v
..........\.......\...\s3_dq_iob.v
..........\.......\...\sdc_constraints.v
..........\.......\...\tap_dly.v
..........\.......\...\test_bench.v
..........\.......\...\top.v
..........\.......\...\ucf_constraints.v
..........\.......\...\wr_gray_cntr.v
..........\.......\template.xml
..........\.hdl\dcm.txt
..........\....\dinfo.xml
..........\....\dsigs.xml
..........\....\filenames.xml
..........\....\hw_details.txt
..........\....\nodcm.txt
..........\....\rtl\addr_gen.vhd
..........\....\...\cal_ctl.vhd
..........\....\...\cal_top.vhd
..........\....\...\clk_dcm.vhd
..........\....\...\cmd_fsm.vhd
..........\....\...\cmp_data.vhd
..........\....\...\controller.vhd
..........\....\...\controller_iobs.vhd
..........\....\...\data_gen.vhd
..........\....\...\data_path.vhd
..........\....\...\data_path_iobs.vhd
..........\....\...\data_read.vhd
..........\....\...\data_read_controller.vhd

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