Using Verilog hdl language of the eight digital control procedures, which for those just learning Verilog hdl language learners, is a good entry procedures, especially procedures for dividing program modules inside, thanks to support.

8位数码管\miaobiao\designer\impl1\designer.log
.........\........\........\.....\miaobiao.adb
.........\........\........\.....\.........dtf\verify.log
.........\........\........\.....\miaobiao.ide_des
.........\........\........\.....\miaobiao.pdb
.........\........\........\.....\miaobiao.pdb.depends
.........\........\........\.....\miaobiao.tcl
.........\........\........\.....\miaobiao_1.ide_des
.........\........\........\.....\.........._fp\$$FlashPro_FPBBALTLPT1.L$$
.........\........\........\.....\.............\miaobiao.log
.........\........\........\.....\.............\miaobiao.pro
.........\........\........\.....\............._1\$$FlashPro_FPBBALTLPT1.L$$
.........\........\........\.....\...............\miaobiao.pro
.........\........\........\.....\..............2\miaobiao.log
.........\........\........\.....\...............\miaobiao.pro
.........\........\........\.....\..............3\$$FlashPro_FPBBALTLPT1.L$$
.........\........\........\.....\...............\miaobiao.log
.........\........\........\.....\...............\miaobiao.pro
.........\........\........\.....\...............\projectData\miaobiao.pdb
.........\........\........\.....\.........fp\$$FlashPro_FPBBALTLPT1.L$$
.........\........\........\.....\...........\miaobiao.log
.........\........\........\.....\...........\miaobiao.pro
.........\........\hdl\miaobiao.v
.........\........\miaobiao.prj
.........\........\simulation\modelsim.ini
.........\........\..........\modelsim.ini.sav
.........\........\.martgen\smartgen.aws
.........\........\.ynthesis\.recordref
.........\........\.........\backup\miaobiao.srr
.........\........\.........\miaobiao.areasrr
.........\........\.........\miaobiao.edn
.........\........\.........\miaobiao.map
.........\........\.........\miaobiao.pdc
.........\........\.........\miaobiao.sdf
.........\........\.........\miaobiao.so
.........\........\.........\miaobiao.srd
.........\........\.........\miaobiao.srm
.........\........\.........\miaobiao.srr
.........\........\.........\miaobiao.srs
.........\........\.........\miaobiao.szr
.........\........\.........\miaobiao.tlg
.........\........\.........\miaobiao_sdc.sdc
.........\........\.........\miaobiao_syn.prj
.........\........\.........\run_options.txt
.........\........\.........\stdout.log
.........\........\.........\.yntmp\miaobiao.plg
.........\........\.........\traplog.tlg
.........\........\viewdraw\vf\project.lst
.........\........\........\viewdraw.ini
.........\........\designer\impl1\miaobiao_1_fp_3\projectData
.........\........\........\.....\miaobiao.dtf
.........\........\........\.....\miaobiao_1_fp
.........\........\........\.....\miaobiao_1_fp_1
.........\........\........\.....\miaobiao_1_fp_2
.........\........\........\.....\miaobiao_1_fp_3
.........\........\........\.....\miaobiao_fp
.........\........\........\.....\simulation
.........\........\........\impl1
.........\........\synthesis\backup
.........\........\.........\coreip
.........\........\.........\syntmp
.........\........\viewdraw\sch
.........\........\........\sym
.........\........\........\vf
.........\........\........\wir
.........\........\component
.........\........\constraint
.........\........\coreconsole
.........\........\designer
.........\........\hdl
.........\........\phy_synthesis
.........\........\simulation
.........\........\smartgen
.........\........\stimulus
.........\........\synthesis
.........\........\viewdraw
.........\miaobiao
8位数码管

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