Verilog-based distributor of design data- the data is public data online distribution of the data sent to different channels as needed on areas of data distribution function of logic circuit known as the data distributor.

allot
.....\allot.prj
.....\component
.....\constraint
.....\coreconsole
.....\designer
.....\........\impl1
.....\........\.....\allot.adb
.....\........\.....\allot.dtf
.....\........\.....\.........\verify.log
.....\........\.....\allot.ide_des
.....\........\.....\allot.pdb
.....\........\.....\allot.pdb.depends
.....\........\.....\allot.tcl
.....\........\.....\allot_fp
.....\........\.....\........\$$FlashPro_FPBBALTLPT1.L$$
.....\........\.....\........\allot.log
.....\........\.....\........\allot.pro
.....\........\.....\........\projectData
.....\........\.....\........\...........\allot.pdb
.....\........\.....\designer.log
.....\........\.....\simulation
.....\hdl
.....\...\allot.v
.....\phy_synthesis
.....\simulation
.....\..........\modelsim.ini
.....\smartgen
.....\........\smartgen.aws
.....\stimulus
.....\synthesis
.....\.........\allot.areasrr
.....\.........\allot.edn
.....\.........\allot.map
.....\.........\allot.pdc
.....\.........\allot.sdf
.....\.........\allot.so
.....\.........\allot.srd
.....\.........\allot.srm
.....\.........\allot.srr
.....\.........\allot.srs
.....\.........\allot.szr
.....\.........\allot.tlg
.....\.........\allot_sdc.sdc
.....\.........\allot_syn.prj
.....\.........\backup
.....\.........\coreip
.....\.........\run_options.txt
.....\.........\stdout.log
.....\.........\syntmp
.....\.........\......\allot.plg
.....\viewdraw
.....\........\sch
.....\........\sym
.....\........\vf
.....\........\..\project.lst
.....\........\viewdraw.ini
.....\........\wir

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