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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 6kb
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  • Author :李****
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Introduction - If you have any usage issues, please Google them yourself
Called a total of four counters (two six-band, two decimal, hexadecimal counter by six experimental procedure to do five simple changes made) string together to form an asynchronous counter, the counter, and by nine serial scan test output. 1Hz pulse with a continuous input, it constitutes a simple timer 1h. With a clear end. Input: Continuous pulse, logic switches output: seven-segment LED.
Packet file list
(Preview for download)
第七次实验\jishuqi10.txt
..........\jishuqi10.vhd
..........\jishuqi_6.txt
..........\jishuqi_6.vhd
..........\time.hex
..........\time.txt
..........\time.vhd
第七次实验
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