Digital Modem

设计\Creativity\channel_choice.v
....\..........\clk_div.v
....\..........\demodulate.v
....\..........\diff_code.v
....\..........\diff_code.v.bak
....\..........\dig_display.v
....\..........\dig_filter.v
....\..........\DPSK.v
....\..........\DPSK_shell.v
....\..........\DPSK_shell.v.bak
....\..........\generate_dm.v
....\..........\generate_dm.vwf
....\..........\get_edge.v
....\..........\instantiation_1to4.v
....\..........\key_buffer.v
....\..........\lcd.vhd
....\..........\lcd.vhd.bak
....\..........\lcdcont.vhd
....\..........\lcdcont.vhd.bak
....\..........\LCM.v
....\..........\LCM_pre.v
....\..........\LCM_pre.v.bak
....\..........\modulate.v
....\..........\my_dff.v
....\..........\my_shift_reg.v
....\..........\my_syn_counter.v
....\..........\my_trigger.v
....\..........\pass_buffer.v
....\..........\pass_buffer_8bit.v
....\..........\phase_counter.v
....\..........\phase_counter.v.bak
....\..........\phase_table.v
....\..........\shift_detect.v
....\..........\synchronize.v
....\Document\CPLD板端口设计.doc
....\........\CPLD母版与模拟电路子板的连接协议.doc
....\........\DPSK数字端集成调试.doc
....\........\DPSK调制解调器设计.doc
....\........\DPSK调制解调器设计文档.doc
....\........\~$LD板端口设计.doc
....\.PSK\Chain1.cdf
....\....\Chain_DPSK.cdf
....\....\channel_choice.vwf
....\....\clk_div.sim.vwf
....\....\clk_div.vwf
....\....\cmp_state.ini
....\....\db\.cbx.xml
....\....\..\add_sub_elh.tdf
....\....\..\add_sub_flh.tdf
....\....\..\add_sub_glh.tdf
....\....\..\add_sub_klh.tdf
....\....\..\decode_nib.tdf
....\....\..\DPSK.asm.qmsg
....\....\..\DPSK.asm_labs.ddb
....\....\..\DPSK.cbx.xml
....\....\..\DPSK.cmp.cdb
....\....\..\DPSK.cmp.hdb
....\....\..\DPSK.cmp.logdb
....\....\..\DPSK.cmp.rdb
....\....\..\DPSK.cmp.tdb
....\....\..\DPSK.cmp0.ddb
....\....\..\DPSK.dbp
....\....\..\DPSK.db_info
....\....\..\DPSK.eco.cdb
....\....\..\DPSK.fit.qmsg
....\....\..\DPSK.hier_info
....\....\..\DPSK.hif
....\....\..\DPSK.map.cdb
....\....\..\DPSK.map.hdb
....\....\..\DPSK.map.logdb
....\....\..\DPSK.map.qmsg
....\....\..\DPSK.pre_map.cdb
....\....\..\DPSK.pre_map.hdb
....\....\..\DPSK.psp
....\....\..\DPSK.pss
....\....\..\DPSK.rtlv.hdb
....\....\..\DPSK.rtlv_sg.cdb
....\....\..\DPSK.rtlv_sg_swap.cdb
....\....\..\DPSK.sgdiff.cdb
....\....\..\DPSK.sgdiff.hdb
....\....\..\DPSK.signalprobe.cdb
....\....\..\DPSK.sim.vwf
....\....\..\DPSK.sld_design_entry.sci
....\....\..\DPSK.sld_design_entry_dsc.sci
....\....\..\DPSK.smp_dump.txt
....\....\..\DPSK.syn_hier_info
....\....\..\DPSK.tan.qmsg
....\....\..\DPSK_cmp.qrpt
....\....\..\DPSK_sim.qrpt
....\....\..\mux_4dc.tdf
....\....\..\mux_d8c.tdf
....\....\..\mux_nkc.tdf
....\....\..\prev_cmp_DPSK.asm.qmsg
....\....\..\prev_cmp_DPSK.fit.qmsg
....\....\..\prev_cmp_DPSK.map.qmsg
....\....\..\prev_cmp_DPSK.tan.qmsg
....\....\..\rom0.hdl.mif
....\....\..\rom0_phase_table_fa73d017.hdl.mif
....\....\..\rom1.hdl.mif
....\....\..\rom10.hdl.mif

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