Ping-pong with the register to achieve cache (Verilog HDL)

ping_pong_buffer\work\_info
................\....\_vmake
................\....\pingpong\_primary.vhd
................\....\........\_primary.dbs
................\....\........\_primary.dat
................\....\........_tb\_primary.vhd
................\....\...........\_primary.dbs
................\....\...........\_primary.dat
................\....\@_opt\voptcxdgv8
................\....\.....\vopt8n1jr5
................\....\.....\vopt56cnr5
................\....\.....\vopt1nntr5
................\....\.....\voptcqriq5
................\....\.....\vopt9q7n74
................\....\.....\vopt57is74
................\....\.....\_deps
................\....\.....\vopty51xr5
................\....\.....\vopttmb0s5
................\....\.....\voptn5n3s5
................\....\.....\vopt1qww74
................\....\.....\vopty67z74
................\....\.....\vopttnh384
................\pingpong.v
................\pingpong_tb.v
................\vsim.wlf
................\ping_pong_buffer.mpf
................\ping_pong_buffer.cr.mti
................\work\_temp
................\....\pingpong
................\....\pingpong_tb
................\....\@_opt
................\work
ping_pong_buffer

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