This is a variable length window averaging filter that uses an MCP3002 ADC with SPI interface to sample an analog input, and has a PWM that can be run through a low-pass filter to produce an analog output. The design was simulated in Modelsim with no problems (although it was not a thorough simulation), and it was successfully implemented on an Altera Cyclone FPGA.

meanFilter\addr16BitCS.vhd
..........\addr1Bit.vhd
..........\addr4Bit.vhd
..........\clkdiv.vhd
..........\mean.vhd
..........\meanFilter.vhd
..........\mux.vhd
..........\PWM.vhd
..........\shifter.vhd
..........\SPI.vhd
..........\tb_clkdiv.vhd
..........\tb_mean.vhd
..........\tb_meanFilter.vhd
..........\tb_PWM.vhd
..........\tb_shifter.vhd
..........\tb_SPI.vhd

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