Havermann source code design and testing source code and Simulation results

work\_info
....\lfsr\_primary.dat
....\....\_primary.vhd
....\....\verilog.asm
....\huffman_enc\_primary.dat
....\...........\_primary.vhd
....\...........\verilog.asm
....\........dec\_primary.dat
....\...........\_primary.vhd
....\...........\verilog.asm
....\generic_fifo_lfsr\_primary.dat
....\.................\_primary.vhd
....\.................\verilog.asm
....\........dpram\_primary.dat
....\.............\_primary.vhd
....\.............\verilog.asm
....\bench_top\_primary.dat
....\.........\_primary.vhd
....\.........\verilog.asm
....\lfsr
....\huffman_enc
....\huffman_dec
....\generic_fifo_lfsr
....\generic_dpram
....\bench_top
work

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