IMPLIMATION OF FIFO,II IS IMPORTANTE FOR LEARNER

FIFO实现\Clock_Dividers_Made_Easy.pdf
........\fifo程序.txt
........\基于Verilog HDL语言的32X8 FIFO设计.PDF
........\异步FIFO结构及FPGA设计.doc
........\高速异步FIFO的实现.PDF
........\FIFO\FIFO.rar
........\....\...._Buffer\FIFO_Syn\FIFO_Buffer.v
........\....\...........\........\FIFO_Syn.cr.mti
........\....\...........\........\FIFO_Syn.mpf
........\....\...........\........\t_FIFO_Buffer.v
........\....\...........\........\vsim.wlf
........\....\...........\........\work\_info
........\....\...........\........\....\t_@f@i@f@o_@buffer\verilog.asm
........\....\...........\........\....\..................\_primary.dat
........\....\...........\........\....\..................\_primary.vhd
........\....\...........\........\....\@f@i@f@o_@buffer\verilog.asm
........\....\...........\........\....\................\_primary.dat
........\....\...........\........\....\................\_primary.vhd
........\....\...........\.....Asyn\FIFO_Buffer.v
........\....\...........\.........\FIFO_Buffer.v.bak
........\....\...........\.........\my_FIFO_Asyn.cr.mti
........\....\...........\.........\my_FIFO_Asyn.mpf
........\....\...........\.........\Ser_Par_Conv_32.v
........\....\...........\.........\t_FIFO_Clock_Domain_Synch.v
........\....\...........\.........\t_FIFO_Clock_Domain_Synch.v.bak
........\....\...........\.........\vsim.wlf
........\....\...........\.........\write_synchronizer.v
........\....\...........\.........\transcript
........\....\...........\.........\work\_info
........\....\...........\.........\....\write_synchronizer\verilog.asm
........\....\...........\.........\....\..................\_primary.dat
........\....\...........\.........\....\..................\_primary.vhd
........\....\...........\.........\....\t_@f@i@f@o_@clock_@domain_@synch\verilog.asm
........\....\...........\.........\....\................................\_primary.dat
........\....\...........\.........\....\................................\_primary.vhd
........\....\...........\.........\....\@ser_@par_@conv_32\verilog.asm
........\....\...........\.........\....\..................\_primary.dat
........\....\...........\.........\....\..................\_primary.vhd
........\....\...........\.........\....\.f@i@f@o_@buffer\verilog.asm
........\....\...........\.........\....\................\_primary.dat
........\....\...........\.........\....\................\_primary.vhd
........\....设计程序\FIFO.doc
........\............\fifo.v
........\............\fifotb.v
........\verilog实例\ADC_16bit.v
........\...........\adder_8bit.v
........\...........\adder_8bit_2.v
........\...........\ALL.V
........\...........\binarytogray.v
........\...........\binarytogray.v.bak
........\...........\cla_8bits.v
........\...........\COMPARE.V
........\...........\dds.v.txt
........\...........\DECODER1.V
........\...........\decoder3x8.v
........\...........\div16.v.txt
........\...........\encoder8x3.v
........\...........\encoder8x3_2.v
........\...........\FIFO.V
........\...........\fifo.v.txt
........\...........\fifo_16x16.v
........\...........\FIFO_2.V
........\...........\framer.v.txt
........\...........\frequency5x2.v
........\...........\full_adder_1.v
........\...........\full_adder_2.v
........\...........\gencrc.v.txt
........\...........\half_adder_1.v
........\...........\half_adder_2.v
........\...........\half_adder_3.v
........\...........\lead_8bits_adder.v
........\...........\lead_8bits_adder2.v
........\...........\MUL16.V
........\...........\mult16.v.txt
........\...........\multi_select_1.v
........\...........\mult_piped_8x8.v
........\...........\mult_select.v
........\...........\MUX8X8.V
........\...........\myrand.c.txt
........\...........\nco.v.txt
........\...........\onehot.v.txt
........\...........\pic.v.txt
........\...........\PLI.TAR
........\...........\RISC8.ZIP
........\...........\sequence_dectect.v
........\...........\SHIFTER.V
........\...........\string.v.txt
........\...........\SYNTHPIC.ZIP
........\...........\TEST.V
........\...........\testing.v.txt
........\...........\test_cla_8bits

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