Design a maximum frequency divider 225, the 50MHz clock as input. Divider can be achieved through the counter, through a 25-bit counter, and then the last one out, then produced a maximum frequency divider 225.

COUNT\binary格雷-二进制.vhd
.....\count分频器.vhd
.....\digit数码管.vhd
.....\reverse_counter可逆计数器.vhd
COUNT

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