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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 1.91mb
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  • Author :刘****
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A kind of DC motor servo system design, including the various control modules of VHDL language
Packet file list
(Preview for download)
zldj\AD1674ctrl.qpf
....\AD1674ctrl.qsf
....\db\fankui1.hif
....\..\AD1674ctrl.db_info
....\..\ADC0809ctrl.cmp.hdb
....\..\ADC0809ctrl.cmp.rdb
....\..\fankui1.psp
....\..\ADC0809ctrl.cmp.tdb
....\..\ADC0809ctrl.sim.qmsg
....\..\fankui1.pss
....\..\AD1674ctrl.cbx.xml
....\..\AD1674ctrl.hif
....\..\AD1674ctrl.asm.qmsg
....\..\AD1674ctrl.tan.qmsg
....\..\AD1674ctrl.hier_info
....\..\ADC0809ctrl.asm.qmsg
....\..\ADC0809ctrl.tan.qmsg
....\..\ADC0809ctrl.fnsim.qmsg
....\..\ADC0809ctrl.cmp0.ddb
....\..\ADC0809ctrl.cmp.cdb
....\..\fankui1.dbp
....\..\AD1674ctrl.psp
....\..\AD1674ctrl.pss
....\..\AD1674ctrl.dbp
....\..\ADC0809ctrl.signalprobe.cdb
....\..\ADC0809ctrl.map.qmsg
....\..\fankui1.db_info
....\..\qiankui.hif
....\..\ADC0809ctrl.fnsim.cdb
....\..\qiankui.psp
....\..\qiankui.pss
....\..\AD1674ctrl.syn_hier_info
....\..\ADC0809ctrl.fnsim.hdb
....\..\ADC0809ctrl.eco.cdb
....\..\qiankui.dbp
....\..\ADC0809ctrl.sld_design_entry_dsc.sci
....\..\ADC0809ctrl.sim.hdb
....\..\ADC0809ctrl.eds_overflow
....\..\ADC0809ctrl.sim.vwf
....\..\ADC0809ctrl.sim.rdb
....\..\bio_polor.hif
....\..\AD1674ctrl.cmp.kpt
....\..\ADD_QF.sim.qmsg
....\..\fankui1.cmp.kpt
....\..\fankui1.fnsim.qmsg
....\..\fankui1.map.qmsg
....\..\dianji.hif
....\..\fankui1.fit.qmsg
....\..\fankui1.cbx.xml
....\..\fankui1.hier_info
....\..\fankui1.rtlv_sg.cdb
....\..\fankui1.rtlv.hdb
....\..\fankui1.pre_map.hdb
....\..\fankui1.rtlv_sg_swap.cdb
....\..\fankui1.pre_map.cdb
....\..\fankui1.map.logdb
....\..\fankui1.sgdiff.cdb
....\..\fankui1.sgdiff.hdb
....\..\fankui1.eco.cdb
....\..\fankui1.syn_hier_info
....\..\fankui1.map.cdb
....\..\fankui1.map.hdb
....\..\fankui1.asm.qmsg
....\..\fankui1.cmp.logdb
....\..\fankui1.sim.qmsg
....\..\fankui1.cmp.cdb
....\..\fankui1.signalprobe.cdb
....\..\fankui1.cmp.tdb
....\..\AD1674ctrl.cmp.rdb
....\..\AD1674ctrl.cmp.tdb
....\..\AD1674ctrl.fnsim.qmsg
....\..\AD1674ctrl.cmp0.ddb
....\..\AD1674ctrl.cmp.cdb
....\..\AD1674ctrl.cmp.hdb
....\..\AD1674ctrl.signalprobe.cdb
....\..\AD1674ctrl.sim.qmsg
....\..\AD1674ctrl.sim.hdb
....\..\fankui1.cmp.hdb
....\..\AD1674ctrl.eco.cdb
....\..\ADD_QF.sim.hdb
....\..\fankui1.cmp.rdb
....\..\AD1674ctrl.fnsim.cdb
....\..\AD1674ctrl.fnsim.hdb
....\..\fankui1.tan.qmsg
....\..\add_sub_0ph.tdf
....\..\fankui1.cmp0.ddb
....\..\qiankui.db_info
....\..\add_sub_2rh.tdf
....\..\add_sub_8rh.tdf
....\..\fankui1.fnsim.cdb
....\..\fankui1.fnsim.hdb
....\..\fankui1.sld_design_entry_dsc.sci
....\..\AD1674ctrl.sim.vwf
....\..\fankui1.sim.hdb
....\..\fankui1.eds_overflow
....\..\fankui1.sim.vwf
....\..\AD1674ctrl.sim.rdb
....\..\fankui1.sim.rdb
....\..\AD1674ctrl.sld_design_entry_dsc.sci
....\..\AD1674ctrl.sld_design_entry.sci
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