ADD

FPGA1\db\FPGA1.asm.qmsg
.....\..\FPGA1.asm_labs.ddb
.....\..\FPGA1.cbx.xml
.....\..\FPGA1.cmp.cdb
.....\..\FPGA1.cmp.hdb
.....\..\FPGA1.cmp.logdb
.....\..\FPGA1.cmp.qrpt
.....\..\FPGA1.cmp.rdb
.....\..\FPGA1.cmp.tdb
.....\..\FPGA1.cmp0.ddb
.....\..\FPGA1.cmp2.ddb
.....\..\FPGA1.dbp
.....\..\FPGA1.db_info
.....\..\FPGA1.eco.cdb
.....\..\FPGA1.eda.qmsg
.....\..\FPGA1.eds_overflow
.....\..\FPGA1.fit.qmsg
.....\..\FPGA1.fnsim.cdb
.....\..\FPGA1.fnsim.hdb
.....\..\FPGA1.fnsim.qmsg
.....\..\FPGA1.hier_info
.....\..\FPGA1.hif
.....\..\FPGA1.map.cdb
.....\..\FPGA1.map.hdb
.....\..\FPGA1.map.logdb
.....\..\FPGA1.map.qmsg
.....\..\FPGA1.pre_map.cdb
.....\..\FPGA1.pre_map.hdb
.....\..\FPGA1.psp
.....\..\FPGA1.rtlv.hdb
.....\..\FPGA1.rtlv_sg.cdb
.....\..\FPGA1.rtlv_sg_swap.cdb
.....\..\FPGA1.sgdiff.cdb
.....\..\FPGA1.sgdiff.hdb
.....\..\FPGA1.signalprobe.cdb
.....\..\FPGA1.sim.hdb
.....\..\FPGA1.sim.qmsg
.....\..\FPGA1.sim.qrpt
.....\..\FPGA1.sim.rdb
.....\..\FPGA1.sim.vwf
.....\..\FPGA1.sld_design_entry.sci
.....\..\FPGA1.sld_design_entry_dsc.sci
.....\..\FPGA1.syn_hier_info
.....\..\FPGA1.tan.qmsg
.....\..\FPGA1.vhd
.....\..\FPGA1.vwf
.....\FPGA1.asm.rpt
.....\FPGA1.done
.....\FPGA1.eda.rpt
.....\FPGA1.fit.eqn
.....\FPGA1.fit.rpt
.....\FPGA1.fit.summary
.....\FPGA1.flow.rpt
.....\FPGA1.map.eqn
.....\FPGA1.map.rpt
.....\FPGA1.map.summary
.....\FPGA1.pin
.....\FPGA1.pof
.....\FPGA1.qpf
.....\FPGA1.qsf
.....\FPGA1.qws
.....\FPGA1.sim.rpt
.....\FPGA1.sof
.....\FPGA1.tan.rpt
.....\FPGA1.tan.summary
.....\quartus_nativelink_simulation.log
.....\simulation\modelsim\FPGA1.vho
.....\..........\........\FPGA1_modelsim.xrf
.....\..........\........\FPGA1_vhd.sdo
.....\..........\modelsim
.....\db
.....\simulation
FPGA1

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