Half adder source code, using VHDL language need to look at

half_adde
.........\cmp_state.ini
.........\db
.........\..\half_adder.asm.qmsg
.........\..\half_adder.cbx.xml
.........\..\half_adder.cmp.cdb
.........\..\half_adder.cmp.hdb
.........\..\half_adder.cmp.qrpt
.........\..\half_adder.cmp.rdb
.........\..\half_adder.cmp.tdb
.........\..\half_adder.cmp0.ddb
.........\..\half_adder.dbp
.........\..\half_adder.db_info
.........\..\half_adder.eco.cdb
.........\..\half_adder.eda.qmsg
.........\..\half_adder.fit.qmsg
.........\..\half_adder.hier_info
.........\..\half_adder.hif
.........\..\half_adder.map.cdb
.........\..\half_adder.map.hdb
.........\..\half_adder.map.qmsg
.........\..\half_adder.pre_map.cdb
.........\..\half_adder.pre_map.hdb
.........\..\half_adder.psp
.........\..\half_adder.rtlv.hdb
.........\..\half_adder.rtlv_sg.cdb
.........\..\half_adder.rtlv_sg_swap.cdb
.........\..\half_adder.sgdiff.cdb
.........\..\half_adder.sgdiff.hdb
.........\..\half_adder.signalprobe.cdb
.........\..\half_adder.sld_design_entry.sci
.........\..\half_adder.sld_design_entry_dsc.sci
.........\..\half_adder.syn_hier_info
.........\..\half_adder.tan.qmsg
.........\..\half_adder_cmp.qrpt
.........\..\half_adder_sim.qrpt
.........\half_adder.asm.rpt
.........\half_adder.done
.........\half_adder.eda.rpt
.........\half_adder.fit.eqn
.........\half_adder.fit.rpt
.........\half_adder.fit.summary
.........\half_adder.flow.rpt
.........\half_adder.map.eqn
.........\half_adder.map.rpt
.........\half_adder.map.summary
.........\half_adder.pin
.........\half_adder.pof
.........\half_adder.ppl
.........\half_adder.qpf
.........\half_adder.qsf
.........\half_adder.qws
.........\half_adder.saf
.........\half_adder.sim.rpt
.........\half_adder.sof
.........\half_adder.tan.rpt
.........\half_adder.tan.summary
.........\half_adder.vhd
.........\half_adder.vwf
.........\half_adder_assignment_defaults.qdf
.........\simulation
.........\..........\vcs
.........\..........\...\half_adder.vo
.........\..........\...\half_adder_v.sdo

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