Hot Search : Source embeded web remote control p2p game More...
Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 114kb
  • Downloaded :0次
  • Author :1****
  • About : Nobody
  • PS : If download it fails, try it again. Download again for free!
Download1 Download2
Don't use download software fo downloading.
If download fail,Try it again for free.
Introduction - If you have any usage issues, please Google them yourself
Speeds up to 130MHz for high-speed data acquisition program source code for the Verilog
Packet file list
(Preview for download)
高速FIFO(Verilog设计)速度高达130Mhz\fifo\src\fifomem.v
...................................\....\...\rptr_empty.v
...................................\....\...\sync_r2w.v
...................................\....\...\sync_w2r.v
...................................\....\...\wptr_full.v
...................................\....\...\fifo1.v
...................................\....\...\test.v
...................................\....\sim.bat
...................................\....\.cript\prepare.do
...................................\....\......\sim.do
...................................\....\......\transcript
...................................\....\......\work\_info
...................................\....\......\....\fifomem\_primary.vhd
...................................\....\......\....\.......\verilog.asm
...................................\....\......\....\.......\_primary.dat
...................................\....\......\....\rptr_empty\_primary.vhd
...................................\....\......\....\..........\verilog.asm
...................................\....\......\....\..........\_primary.dat
...................................\....\......\....\sync_r2w\_primary.vhd
...................................\....\......\....\........\verilog.asm
...................................\....\......\....\........\_primary.dat
...................................\....\......\....\.....w2r\_primary.vhd
...................................\....\......\....\........\verilog.asm
...................................\....\......\....\........\_primary.dat
...................................\....\......\....\wptr_full\_primary.vhd
...................................\....\......\....\.........\verilog.asm
...................................\....\......\....\.........\_primary.dat
...................................\....\......\....\fifo1\_primary.vhd
...................................\....\......\....\.....\verilog.asm
...................................\....\......\....\.....\_primary.dat
...................................\....\......\....\test\_primary.vhd
...................................\....\......\....\....\verilog.asm
...................................\....\......\....\....\_primary.dat
...................................\....\......\run.f
...................................\....\......\t1
...................................\....\......\t2
...................................\....\......\t3
...................................\....\......\t4.rc
...................................\....\......\fifo.fsdb
...................................\....\nlint.bat
...................................\....\debussy\Debussy.exeLog\debussy.rc
...................................\....\.......\..............\turbo.log
...................................\....\.......\..............\Debussy.exe.cmd
...................................\....\.......\..............\compiler.log
...................................\....\.......\..............\ToNetlist.log
...................................\....\.......\..............\Debussy.exe.cmd.bak
...................................\....\.......\debussy.rc
...................................\....\nlint\nLint.exeLog\nLint.rc
...................................\....\.....\............\turbo.log
...................................\....\.....\............\compiler.log
...................................\....\.....\nLint.rc
...................................\....\.....\nLint.ds
...................................\....\.....\nlReport.rdb
...................................\使用说明请参看右侧注释====〉〉.txt
...................................\fifo\script\work\fifomem
...................................\....\......\....\rptr_empty
...................................\....\......\....\sync_r2w
...................................\....\......\....\sync_w2r
...................................\....\......\....\wptr_full
...................................\....\......\....\fifo1
...................................\....\......\....\test
...................................\....\......\work
...................................\....
Related instructions
  • We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
  • The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
  • Please use Winrar for decompression tools
  • If download fail, Try it againg or Feedback to us.
  • If downloaded content did not match the introduction, Feedback to us,Confirm and will be refund.
  • Before downloading, you can inquire through the uploaded person information

Nothing.

Post Comment
*Quick comment Recommend Not bad Password Unclear description Not source
Lost files Unable to decompress Bad
*Content :
*Captcha :
CodeBus is one of the largest source code repositories on the Internet!
Contact us :
1999-2046 CodeBus All Rights Reserved.