Synchronous FIFO based EasyFPGA030 Design and Implementation of Engineering.

基于EasyFPGA030的同步FIFO设计工程文件\FIFO\designer\impl1\designer.log
.....................................\....\........\.....\designer_gen_ba.log
.....................................\....\........\.....\designer_synth_check.log
.....................................\....\........\.....\display.ide_des
.....................................\....\........\.....\fifo.ide_des
.....................................\....\........\.....\key.ide_des
.....................................\....\........\.....\main.adb
.....................................\....\........\.....\.....dtf\verify.log
.....................................\....\........\.....\main.ide_des
.....................................\....\........\.....\main.pdb
.....................................\....\........\.....\main.pdb.depends
.....................................\....\........\.....\main.tcl
.....................................\....\........\.....\main_ba.sdf
.....................................\....\........\.....\main_ba.sdf_max.csd
.....................................\....\........\.....\main_ba.v
.....................................\....\........\.....\.....fp\$$FlashPro_FPBBALTLPT1.L$$
.....................................\....\........\.....\.......\main.log
.....................................\....\........\.....\.......\main.pro
.....................................\....\........\.....\.......\projectData\main.pdb
.....................................\....\........\.....\multiply.ide_des
.....................................\....\........\.....\simulation\postlayout\main\verilog.psm
.....................................\....\........\.....\..........\..........\....\_primary.dat
.....................................\....\........\.....\..........\..........\....\_primary.dbs
.....................................\....\........\.....\..........\..........\....\_primary.vhd
.....................................\....\........\.....\..........\..........\stimulus\verilog.psm
.....................................\....\........\.....\..........\..........\........\_primary.dat
.....................................\....\........\.....\..........\..........\........\_primary.dbs
.....................................\....\........\.....\..........\..........\........\_primary.vhd
.....................................\....\........\.....\..........\..........\tb_clock_minmax\verilog.psm
.....................................\....\........\.....\..........\..........\...............\_primary.dat
.....................................\....\........\.....\..........\..........\...............\_primary.dbs
.....................................\....\........\.....\..........\..........\...............\_primary.vhd
.....................................\....\........\.....\..........\..........\.estbench\verilog.psm
.....................................\....\........\.....\..........\..........\.........\_primary.dat
.....................................\....\........\.....\..........\..........\.........\_primary.dbs
.....................................\....\........\.....\..........\..........\.........\_primary.vhd
.....................................\....\........\.....\..........\..........\_info
.....................................\....\........\.....\..........\..........\_vmake
.....................................\....\final.prj
.....................................\....\hdl\display.v
.....................................\....\...\fifo.v
.....................................\....\...\key.v
.....................................\....\...\main.v
.....................................\....\...\multiply.v
.....................................\....\...\timming.v
.....................................\....\smartgen\smartgen.aws
.....................................\....\.timulus\BtimErrors.log
.....................................\....\........\files_to_build.txt
.....................................\....\........\main.dsk
.....................................\....\........\main.hpj
.....................................\....\........\main_tbench.bk
........

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