The code functions as the input clock frequency of 1.5 features. Procedure quartusII 8.1 compiler, use the verilog language. Bin Jie in science and technology* BJTECH company' s development board based on altera epm240 verification. (Development Board web site http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm) in need of friends can download reference

halfclk\cmp_state.ini
.......\db\halfclk.db_info
.......\..\halfclk.eco.cdb
.......\..\halfclk.sld_design_entry.sci
.......\..\halfclk_cmp.qrpt
.......\halfclk.asm.rpt
.......\halfclk.cdf
.......\halfclk.done
.......\halfclk.fit.eqn
.......\halfclk.fit.rpt
.......\halfclk.fit.summary
.......\halfclk.flow.rpt
.......\halfclk.map.eqn
.......\halfclk.map.rpt
.......\halfclk.map.summary
.......\halfclk.pin
.......\halfclk.pof
.......\halfclk.qpf
.......\halfclk.qsf
.......\halfclk.qws
.......\halfclk.tan.rpt
.......\halfclk.tan.summary
.......\halfclk.v
.......\halfclk_assignment_defaults.qdf
.......\db
halfclk

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