Control of operation of the SDRAM FPGA source code, using VERILOG hardware description language, the file contains a total of: hostcont.v, inc.h, pinouts.ucf, sdram.v, top.v, tst_inc.h

FPGA_SDRAM\hostcont.v
..........\inc.h
..........\pinouts.ucf
..........\sdram.v
..........\sdramcnt.v
..........\sdram_controller.npl
..........\top.v
..........\tst_inc.h
FPGA_SDRAM

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