The file is a ram in the development process. . . Second process procedures are written in my own. Verification result is correct. . .

RAM\ADD8B.bsf
...\ADD8B.vhd
...\ADD8B.vhd.bak
...\ADDRESS.bsf
...\ADDRESS.vhd
...\ADDRESS.vhd.bak
...\db\altsyncram_06q1.tdf
...\..\altsyncram_12e1.tdf
...\..\altsyncram_47r1.tdf
...\..\altsyncram_6h92.tdf
...\..\altsyncram_96c1.tdf
...\..\altsyncram_el72.tdf
...\..\altsyncram_nmf1.tdf
...\..\altsyncram_s5b2.tdf
...\..\decode_aoi.tdf
...\..\prev_cmp_testRAMWR.asm.qmsg
...\..\prev_cmp_testRAMWR.fit.qmsg
...\..\prev_cmp_testRAMWR.map.qmsg
...\..\prev_cmp_testRAMWR.qmsg
...\..\prev_cmp_testRAMWR.sim.qmsg
...\..\prev_cmp_testRAMWR.tan.qmsg
...\..\testRAMWR.db_info
...\..\testRAMWR.eco.cdb
...\..\testRAMWR.sim.cvwf
...\..\testRAMWR.sld_design_entry.sci
...\..\wed.wsf
...\Delay.vhd
...\Delay.vhd.bak
...\DOUBLRAM.bsf
...\DOUBLRAM.cmp
...\DOUBLRAM.inc
...\DOUBLRAM.qip
...\DOUBLRAM.vhd
...\DOUBLRAM_inst.vhd
...\DOUBLRAM_wave0.jpg
...\DOUBLRAM_wave1.jpg
...\DOUBLRAM_waveforms.html
...\FIFO.bsf
...\FIFO.cmp
...\FIFO.inc
...\FIFO.qip
...\FIFO.vhd
...\fifo3.vhd
...\fifo3.vhd.bak
...\FIFO_inst.vhd
...\FIFO_wave0.jpg
...\FIFO_wave1.jpg
...\FIFO_waveforms.html
...\IIPORTRAM.bsf
...\IIPORTRAM.cmp
...\IIPORTRAM.inc
...\IIPORTRAM.qip
...\IIPORTRAM.vhd
...\IIPORTRAM_inst.vhd
...\IIPORTRAM_wave0.jpg
...\IIPORTRAM_wave1.jpg
...\IIPORTRAM_waveforms.html
...\RAMWR.bsf
...\RAMWR.cmp
...\RAMWR.inc
...\RAMWR.qip
...\RAMWR.vhd
...\RAMWR_inst.vhd
...\RAMWR_wave0.jpg
...\RAMWR_wave1.jpg
...\RAMWR_waveforms.html
...\testRAMWR.asm.rpt
...\testRAMWR.bdf
...\testRAMWR.done
...\testRAMWR.fit.rpt
...\testRAMWR.fit.smsg
...\testRAMWR.fit.summary
...\testRAMWR.flow.rpt
...\testRAMWR.jdi
...\testRAMWR.map.rpt
...\testRAMWR.map.summary
...\testRAMWR.pin
...\testRAMWR.pof
...\testRAMWR.qpf
...\testRAMWR.qsf
...\testRAMWR.qws
...\testRAMWR.sim.rpt
...\testRAMWR.sof
...\testRAMWR.tan.rpt
...\testRAMWR.tan.summary
...\WAVEDATA\testRAMWR.vwf
...\db
...\WAVEDATA
RAM

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