It s a vhdl program. Simulates a traffic light controllet using a Cyclone II FPGA

TLC.asm.rpt
TLC.done
TLC.fit.eqn
TLC.fit.rpt
TLC.fit.summary
TLC.flow.rpt
TLC.map.eqn
TLC.map.rpt
TLC.map.summary
TLC.pin
TLC.pof
TLC.qpf
TLC.qsf
TLC.qws
TLC.sof
TLC.tan.rpt
TLC.tan.summary
TLC.vhd
TLC.vhd.bak
db\prev_cmp_TLC.asm.qmsg
..\prev_cmp_TLC.fit.qmsg
..\prev_cmp_TLC.map.qmsg
..\prev_cmp_TLC.qmsg
..\prev_cmp_TLC.tan.qmsg
..\TLC.asm.qmsg
..\TLC.asm_labs.ddb
..\TLC.cbx.xml
..\TLC.cmp.bpm
..\TLC.cmp.cdb
..\TLC.cmp.ecobp
..\TLC.cmp.hdb
..\TLC.cmp.kpt
..\TLC.cmp.logdb
..\TLC.cmp.rdb
..\TLC.cmp.tdb
..\TLC.cmp0.ddb
..\TLC.cmp_merge.kpt
..\TLC.db_info
..\TLC.eco.cdb
..\TLC.fit.qmsg
..\TLC.hier_info
..\TLC.hif
..\TLC.lpc.html
..\TLC.lpc.rdb
..\TLC.lpc.txt
..\TLC.map.bpm
..\TLC.map.cdb
..\TLC.map.ecobp
..\TLC.map.hdb
..\TLC.map.kpt
..\TLC.map.logdb
..\TLC.map.qmsg
..\TLC.map_bb.cdb
..\TLC.map_bb.hdb
..\TLC.map_bb.logdb
..\TLC.pre_map.cdb
..\TLC.pre_map.hdb
..\TLC.rpp.qmsg
..\TLC.rtlv.hdb
..\TLC.rtlv_sg.cdb
..\TLC.rtlv_sg_swap.cdb
..\TLC.sgate.rvd
..\TLC.sgate_sm.rvd
..\TLC.sgdiff.cdb
..\TLC.sgdiff.hdb
..\TLC.sld_design_entry.sci
..\TLC.sld_design_entry_dsc.sci
..\TLC.syn_hier_info
..\TLC.tan.qmsg
..\TLC.tis_db_list.ddb
..\TLC.tmw_info
incremental_db\compiled_partitions\TLC.root_partition.cmp.atm
..............\...................\TLC.root_partition.cmp.dfp
..............\...................\TLC.root_partition.cmp.hdbx
..............\...................\TLC.root_partition.cmp.kpt
..............\...................\TLC.root_partition.cmp.logdb
..............\...................\TLC.root_partition.cmp.rcf
..............\...................\TLC.root_partition.map.atm
..............\...................\TLC.root_partition.map.dpi
..............\...................\TLC.root_partition.map.hdbx
..............\...................\TLC.root_partition.map.kpt
..............\README
serv_req_info.txt
incremental_db\compiled_partitions
db
incremental_db

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