With a clear end to enable and D flip-flop, Verilog implementation, there is experimental documentation.

74hc74.pdf
74hc74
......\component
......\constraint
......\coreconsole
......\designer
......\........\impl1
......\........\.....\designer.log
......\........\.....\d_ff.adb
......\........\.....\d_ff.dtf
......\........\.....\........\verify.log
......\........\.....\d_ff.ide_des
......\........\.....\d_ff.pdb
......\........\.....\d_ff.pdb.depends
......\........\.....\d_ff.tcl
......\........\.....\d_ff_fp
......\........\.....\.......\$$FlashPro_07294.L$$
......\........\.....\.......\d_ff.log
......\........\.....\.......\d_ff.pro
......\........\.....\.......\projectData
......\........\.....\.......\...........\d_ff.pdb
......\........\.....\simulation
......\d_ff.prj
......\hdl
......\...\d_ff.v
......\phy_synthesis
......\simulation
......\..........\modelsim.ini
......\..........\modelsim.ini.sav
......\smartgen
......\........\smartgen.aws
......\stimulus
......\synthesis
......\.........\backup
......\.........\......\d_ff.srr
......\.........\coreip
......\.........\d_ff.areasrr
......\.........\d_ff.edn
......\.........\d_ff.htm
......\.........\d_ff.map
......\.........\d_ff.pdc
......\.........\d_ff.sdf
......\.........\d_ff.so
......\.........\d_ff.srd
......\.........\d_ff.srm
......\.........\d_ff.srr
......\.........\d_ff.srs
......\.........\d_ff.szr
......\.........\d_ff.tlg
......\.........\d_ff_sdc.sdc
......\.........\d_ff_syn.prj
......\.........\run_options.txt
......\.........\stdout.log
......\.........\syntmp
......\.........\......\d_ff.plg
......\.........\......\d_ff_flink.htm
......\.........\......\d_ff_srr.htm
......\.........\......\d_ff_toc.htm
......\viewdraw
......\........\sch
......\........\sym
......\........\vf
......\........\..\project.lst
......\........\viewdraw.ini
......\........\wir

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