DDS generation module based on Altera FPGA

my_dds\add373.bsf
......\add373.inc
......\add373.v
......\add373.v.bak
......\buffer.bsf
......\buffer.v
......\bus_connect.bsf
......\bus_connect.v
......\count.bsf
......\count.v
......\dds.bdf
......\DDS_HAO
......\DDS_HAO.BIN
......\DDS_HAO.C
......\DDS_HAO.HEX
......\DDS_HAO.LST
......\DDS_HAO.M51
......\DDS_HAO.OBJ
......\dds_verilog.asm.rpt
......\dds_verilog.cdf
......\dds_verilog.done
......\dds_verilog.dpf
......\dds_verilog.fit.rpt
......\dds_verilog.fit.smsg
......\dds_verilog.fit.summary
......\dds_verilog.flow.rpt
......\dds_verilog.map.rpt
......\dds_verilog.map.smsg
......\dds_verilog.map.summary
......\dds_verilog.pin
......\dds_verilog.pof
......\dds_verilog.qpf
......\dds_verilog.qsf
......\dds_verilog.qws
......\dds_verilog.sof
......\dds_verilog.tan.rpt
......\dds_verilog.tan.summary
......\fenpin.bsf
......\fenpin.v
......\Hex1.hex
......\Hex1.qpf
......\Hex1.qsf
......\TEMP.LST
......\WAVE.LIN
......\xgh.bsf
......\xgh.v
......\xgh_bb.v
......\xgh_wave0.jpg
......\xgh_waveforms.html
......\yima138.bsf
......\yima138.v
......\yima138.v.bak
......\db\altsyncram_5t21.tdf
......\..\altsyncram_dt21.tdf
......\..\altsyncram_etp1.tdf
......\..\altsyncram_j331.tdf
......\..\altsyncram_sd61.tdf
......\..\altsyncram_vsl1.tdf
......\..\dds_verilog.asm.qmsg
......\..\dds_verilog.cbx.xml
......\..\dds_verilog.cmp.bpm
......\..\dds_verilog.cmp.cdb
......\..\dds_verilog.cmp.ecobp
......\..\dds_verilog.cmp.hdb
......\..\dds_verilog.cmp.logdb
......\..\dds_verilog.cmp.rdb
......\..\dds_verilog.cmp.tdb
......\..\dds_verilog.cmp0.ddb
......\..\dds_verilog.cmp_bb.cdb
......\..\dds_verilog.cmp_bb.hdb
......\..\dds_verilog.cmp_bb.logdb
......\..\dds_verilog.cmp_bb.rcf
......\..\dds_verilog.dbp
......\..\dds_verilog.db_info
......\..\dds_verilog.eco.cdb
......\..\dds_verilog.fit.qmsg
......\..\dds_verilog.hier_info
......\..\dds_verilog.hif
......\..\dds_verilog.map.bpm
......\..\dds_verilog.map.cdb
......\..\dds_verilog.map.ecobp
......\..\dds_verilog.map.hdb
......\..\dds_verilog.map.logdb
......\..\dds_verilog.map.qmsg
......\..\dds_verilog.map_bb.cdb
......\..\dds_verilog.map_bb.hdb
......\..\dds_verilog.map_bb.logdb
......\..\dds_verilog.pre_map.cdb
......\..\dds_verilog.pre_map.hdb
......\..\dds_verilog.psp
......\..\dds_verilog.pss
......\..\dds_verilog.rtlv.hdb
......\..\dds_verilog.rtlv_sg.cdb
......\..\dds_verilog.rtlv_sg_swap.cdb
......\..\dds_verilog.sgdiff.cdb
......\..\dds_verilog.sgdiff.hdb
......\..\dds_verilog.signalprobe.cdb
......\..\dds_verilog.sld_design_entry.sci
......\..\dds_verilog.sld_design_entry_dsc.sci
......\..\dds_verilog.syn_hier_info

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．