The document is based on fpga' s RS (204.188) decoder verilong source code, use the Quartus II development environment, has been compiled by the need to download the compiler can resume their work using

Filename	Size	Update
fpga_verilog_RS(204	188)doecder\BM_KES.v
...............................\CheinSearch.v
...............................\ff_mul.v
...............................\forney.v
...............................\ROM_INV.mif
...............................\rom_inv.v
...............................\rom_power.mif
...............................\rom_power.v
...............................\RS(204	188)译码器说明.txt
...............................\rs_decoder.v
...............................\SyndromeCalc.v
fpga_verilog_RS(204	188)doecder

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