Fpga using Verilog language to achieve VGA reality, in some characters on the display.

DF2C8_05_VGA\PRJ\char_rom.v
............\...\db\prev_cmp_VGA.asm.qmsg
............\...\..\prev_cmp_VGA.fit.qmsg
............\...\..\prev_cmp_VGA.map.qmsg
............\...\..\prev_cmp_VGA.qmsg
............\...\..\prev_cmp_VGA.tan.qmsg
............\...\..\VGA.asm.qmsg
............\...\..\VGA.asm_labs.ddb
............\...\..\VGA.cbx.xml
............\...\..\VGA.cmp.bpm
............\...\..\VGA.cmp.cdb
............\...\..\VGA.cmp.ecobp
............\...\..\VGA.cmp.hdb
............\...\..\VGA.cmp.kpt
............\...\..\VGA.cmp.logdb
............\...\..\VGA.cmp.rdb
............\...\..\VGA.cmp.tdb
............\...\..\VGA.cmp0.ddb
............\...\..\VGA.cmp2.ddb
............\...\..\VGA.cmp_merge.kpt
............\...\..\VGA.db_info
............\...\..\VGA.eco.cdb
............\...\..\VGA.fit.qmsg
............\...\..\VGA.hier_info
............\...\..\VGA.hif
............\...\..\VGA.lpc.html
............\...\..\VGA.lpc.rdb
............\...\..\VGA.lpc.txt
............\...\..\VGA.map.bpm
............\...\..\VGA.map.cdb
............\...\..\VGA.map.ecobp
............\...\..\VGA.map.hdb
............\...\..\VGA.map.kpt
............\...\..\VGA.map.logdb
............\...\..\VGA.map.qmsg
............\...\..\VGA.map_bb.cdb
............\...\..\VGA.map_bb.hdb
............\...\..\VGA.map_bb.logdb
............\...\..\VGA.pre_map.cdb
............\...\..\VGA.pre_map.hdb
............\...\..\VGA.rtlv.hdb
............\...\..\VGA.rtlv_sg.cdb
............\...\..\VGA.rtlv_sg_swap.cdb
............\...\..\VGA.sgdiff.cdb
............\...\..\VGA.sgdiff.hdb
............\...\..\VGA.sld_design_entry.sci
............\...\..\VGA.sld_design_entry_dsc.sci
............\...\..\VGA.syn_hier_info
............\...\..\VGA.tan.qmsg
............\...\..\VGA.tis_db_list.ddb
............\...\..\VGA.tmw_info
............\...\incremental_db\compiled_partitions\VGA.root_partition.cmp.atm
............\...\..............\...................\VGA.root_partition.cmp.dfp
............\...\..............\...................\VGA.root_partition.cmp.hdbx
............\...\..............\...................\VGA.root_partition.cmp.kpt
............\...\..............\...................\VGA.root_partition.cmp.logdb
............\...\..............\...................\VGA.root_partition.cmp.rcf
............\...\..............\...................\VGA.root_partition.map.atm
............\...\..............\...................\VGA.root_partition.map.dpi
............\...\..............\...................\VGA.root_partition.map.hdbx
............\...\..............\...................\VGA.root_partition.map.kpt
............\...\..............\README
............\...\sync_gen_50m.v
............\...\VGA.asm.rpt
............\...\VGA.bdf
............\...\VGA.cdf
............\...\VGA.done
............\...\VGA.fit.rpt
............\...\VGA.fit.smsg
............\...\VGA.fit.summary
............\...\VGA.flow.rpt
............\...\VGA.map.rpt
............\...\VGA.map.summary
............\...\VGA.merge.rpt
............\...\VGA.pin
............\...\VGA.pof
............\...\VGA.qpf
............\...\VGA.qsf
............\...\VGA.qws
............\...\VGA.sof
............\...\VGA.tan.rpt
............\...\VGA.tan.summary
............\...\vga3.bsf
............\...\vga3.v
............\...\VGA_assignment_defaults.qdf
............\例程简要说明.pdf
............\PRJ\incremental_db\compiled_partitions
............\...\db
............\...\incremental_db
............\PRJ
DF2C8_05_VGA

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